DataSheet26.com

даташит AD5551 PDF электронных компонентов


AD5551 - Analog Devices - 5 V/ Serial-Input Voltage-Output/ 14-Bit DACs

Номер произв AD5551
Описание 5 V/ Serial-Input Voltage-Output/ 14-Bit DACs
Производители Analog Devices
логотип Analog Devices логотип 
предварительный просмотр
1Page
		

No Preview Available !

AD5551 Даташит, Описание, Даташиты
a
5 V, Serial-Input
Voltage-Output, 14-Bit DACs
AD5551/AD5552
FEATURES
Full 14-Bit Performance
5 V Single Supply Operation
Low Power
Fast Settling Time
Unbuffered Voltage Output Capable of Driving 60 k
Loads Directly
SPI™/QSPI™/MICROWIRE™-Compatible Interface
Standards
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
GENERAL DESCRIPTION
The AD5551 and AD5552 are single, 14-bit, serial input, voltage
output DACs that operate from a single 5 V ± 10% supply.
The AD5551 and AD5552 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
These DACs provide 14-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.
With an external op amp the AD5552 can be operated in bipo-
lar mode generating a ± VREF output swing. The AD5552 also
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity. For higher precision
applications, please refer to 16-bit DACs AD5541, AD5542,
and AD5544.
The AD5551 and AD5552 are available in an SO package.
FUNCTIONAL BLOCK DIAGRAMS
VREF
AD5551
VDD
14-BIT DAC
VOUT
CS
DIN
SCLK
CONTROL
LOGIC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
AGND
DGND
VREFF
VREFS
CS
LDAC
SCLK
DIN
AD5552
RINV
CONTROL
LOGIC
VDD
RFB
14-BIT DAC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
RFB
INV
VOUT
AGNDF
AGNDS
DGND
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
The AD5551 and AD5552 are fully specified and guaranteed
for a single 5 V ± 10% supply.
2. Low Power Consumption.
Typically 1.5 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered output capable of driving 60 kloads, which
reduces power consumption as there is no internal buffer
to drive.
5. Power-On Reset Circuitry.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
--------------------------------------------

No Preview Available !

AD5551 Даташит, Описание, Даташиты
AD5551/AD5552–SPECIFICATIONS (VDD = 5 V ؎ 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications
TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Min Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
Relative Accuracy, INL
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Zero Code Error
Zero Code Temperature Coefficient
AD5552
Bipolar Resistor Matching
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
14
–1.75
0
± 0.15
± 0.15
–0.3
± 0.1
0.1
± 0.05
1.000
± 0.0015
± 0.25
± 0.2
± 1.0
± 0.8
0
0.5
± 0.0152
± 2.5
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
/
%
LSB
ppm/°C
B Grade
Guaranteed Monotonic
RFB/RINV, Typically RFB = RINV = 28 k
Ratio Error
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUT
Reference Input Range
Reference Input Resistance2
0
–VREF
1
25
10
10
6.25
2.0
9
7.5
VREF – 1 LSB
VREF – 1 LSB
± 1.0
V
V
µs
V/µs
nV-s
nV-s
k
LSB
VDD
V
k
k
Unipolar Operation
AD5552 Bipolar Operation
to 1/2 LSB of FS, CL = 10 pF
CL = 10 pF, Measured from 0% to 63%
1 LSB Change Around the Major Carry
All 1s Loaded to DAC, VREF = 2.5 V
Tolerance Typically 20%
VDD ± 10%
Unipolar Operation
AD5552, Bipolar Operation
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Input Capacitance3
Hysteresis Voltage3
2.4
0.4
±1
0.8
10
µA
V
V
pF
V
REFERENCE
Reference –3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
POWER REQUIREMENTS
VDD
IDD
Power Dissipation
1.3
1
92
75
120
4.50
0.3
1.5
5.50
1.1
6.05
MHz
mV p-p
dB
pF
pF
All 1s Loaded
All 0s Loaded, VREF = 1 V p-p at 100 kHz
Code 0000H
Code 3FFFH
V
mA
mW
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Reference input resistance is code-dependent, minimum at 2555H.
3Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2– REV. 0
--------------------------------------------

No Preview Available !

AD5551 Даташит, Описание, Даташиты
AD5551/AD5552
TIMING CHARACTERISTICS1, 2 (VDD = 5 V ؎ 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
otherwise noted.)
Parameter
Limit at TMIN, TMAX
All Versions
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
25
40
20
20
15
15
35
20
15
0
30
30
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold Time
SCLK High to CS High Hold Time
Data Setup Time
Data Hold Time
LDAC Pulsewidth
CS High to LDAC Low Setup
CS High Time Between Active Periods
NOTES
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
Specifications subject to change without notice.
SCLK
CS
DIN
LDAC*
t6
t4
t 12
t8
DB13
t9
t1
t2 t3
t5
t7
DB0
t 11
t 10
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 1. Timing Diagram
REV. 0
–3–
--------------------------------------------





Всего страниц 12 Pages
Скачать PDF[ AD5551.PDF Даташит ]

Ссылка Поделиться

Related Datasheets

Номер в каталогеОписаниеПроизводители
AD5551  AD5551 Даташит - Analog Devices5 V/ Serial-Input Voltage-Output/ 14-Bit DACsAnalog Devices
Analog Devices
AD5552  AD5552 Даташит - Analog Devices5 V/ Serial-Input Voltage-Output/ 14-Bit DACsAnalog Devices
Analog Devices
AD5553  AD5553 Даташит - Analog DevicesCurrent Output/ Serial Input/ 16-/14-Bit DACAnalog Devices
Analog Devices
AD5554  AD5554 Даташит - Analog DevicesQuad/ Current-Output Serial-Input/ 16-Bit/14-Bit DACsAnalog Devices
Analog Devices
AD5555  AD5555 Даташит - Analog Devices16-/14-Bit DACsAnalog Devices
Analog Devices
AD5556  AD5556 Даташит - Analog Devices16-/14-Bit Multiplying DACAnalog Devices
Analog Devices


Номер в каталоге Описание Производители
157UD2

Dual op amp

ETC 1
ETC 1
6MBP200RA-060

Intelligent Power Module

Fuji Electric
Fuji Electric
ADF41020

18 GHz Microwave PLL Synthesizer

Analog Devices
Analog Devices
AN-SY6280

Low Loss Power Distribution Switch

Silergy
Silergy
AP6354

2x2 WiFi + Bluetooth4.1 Module

AMPAK
AMPAK

Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z




DataSheet26.com    |    2017    |   Контакты    |    English