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M-8880 - Clare Inc. - M-8880 DTMF Transceiver

Номер произв M-8880
Описание M-8880 DTMF Transceiver
Производители Clare Inc.
логотип Clare  Inc. логотип 
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M-8880 Даташит, Описание, Даташиты
M-8880 DTMF Transceiver
· Advanced CMOS technology for low power consump-
tion and increased noise immunity
· Complete DTMF transmitter/receiver in a single chip
· Standard 6500/6800 series microprocessor port
· Central office quality and performance
· Adjustable guard time
· Automatic tone burst mode
· Call progress mode
· Single +5 Volt power supply
· 20-pin DIP and SOIC packages
· 2 MHz microprocessor port operation
· Inexpensive 3.58 MHz crystal
· No continuous f2 clock required, only strobe
· Applications include: paging systems, repeater sys-
tems/mobile radio, interconnect dialers, PBX systems,
computer systems, fax machines, pay telephones,
credit card verification
The M-8880 is a complete DTMF Transmitter/Receiver that fea-
tures adjustable guard time, automatic tone burst mode, call
progress mode, and a fully compatible 6500/6800 microproces-
sor interface. The receiver portion is based on the industry stan-
dard M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for
low-distortion, highly accurate DTMF signaling. Tone bursts can
be transmitted with precise timing by making use of the auto-
matic tone burst mode. To analyze call progress tones, a call
progress filter can be selected by an external microprocessor.
Figure 1 Pin Diagram
Functional Description
M-8880 functions consist of a high-performance DTMF receiver
with an internal gain setting amplifier and a DTMF generator that
contains a tone burst counter for generating precise tone bursts
and pauses. The call progress mode, when selected, allows the
detection of call progress tones. A standard 6500/6800 series
microprocessor interface allows access to an internal status
register, two control registers, and two data registers.
Input Configuration
The input arrangement consists of a differential input opera-
tional amplifier and bias sources (VREF) for biasing the amplifier
inputs at VDD/2. Provisions are made for the connection of a
feedback resistor to the op-amp output (GS) for gain adjust-
40-406-00012, Rev. G
Figure 2 Block Diagram
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M-8880 Даташит, Описание, Даташиты
M-8880
Figure 3 Single-Ended Input Configuration
Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be
connected as shown in Figure 3. Figure 4 shows the necessary
connections for a differential input configuration.
Receiver Section
The low and high group tones are separated by applying the
DTMF signal to the inputs of two sixth-order switched capacitor
bandpass filters with bandwidths that correspond to the low and
high group frequencies listed in Table 2. The low group filter in-
corporates notches at 350 and 440 Hz, providing excellent dial
tone rejection. Each filter output is followed by a single-order
switched capacitor filter that smooths the signals prior to limiting.
Limiting is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals. The com-
parator outputs provide full-rail logic swings at the incoming
DTMF signal frequencies.
A decoder employs digital counting techniques to determine the
frequencies of the incoming tones, and to verify that they corre-
spond to standard DTMF frequencies. A complex averaging al-
gorithm protects against tone simulation by extraneous signals
(such as voice), while tolerating small deviations in frequency.
The algorithm provides an optimum combination of immunity to
talkoff with tolerance to interfering frequencies (third tones) and
noise. When the detector recognizes the presence of two valid
tones (referred to as “signal condition”), the early steering (ESt)
output goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Steering Circuit: Before a decoded tone pair is registered, the
receiver checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed by an ex-
ternal RC time constant driven by ESt. A logic high on ESt
Table 1 Pin Functions
Name
IN+
IN-
GS
VREF
VSS
OSC1
OSC2
TONE
R/W
CS
RS0
φ2
IRQ/CP
D0 - D3
ESt
St/GT
VDD
Description
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail.
Negative power supply input.
DTMF clock/oscillator input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL
compatible.
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Table 6. TTL compatible.
System clock input. May be continuous or strobed only during read or write. TTL compatible.
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and inter-
rupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any
momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St.
Positive power supply input.
40-406-00012, Rev. G
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M-8880 Даташит, Описание, Даташиты
M-8880
causes VC (see Figure 5) to rise as the capacitor discharges.
Provided that the signal condition is maintained (ESt remains
high) for the validation period (tGTP), VC reaches the threshold
(VTSt) of the steering logic to register the tone pair, latching its
corresponding 4-bit code (see Table 2) into the receive data reg-
ister.
Table 2 Tone Encoding/Decoding
FLOW FHIGH Digit
D3
D2
D1
697 1209
1
0
0
0
697 1336
2
0
0
1
697 1477
3
0
0
1
770 1209
4
0
1
0
770 1336
5
0
1
0
770 1477
6
0
1
1
852 1209
7
0
1
1
852 1336
8
1
0
0
852 1477
9
1
0
0
941 1336
0
1
0
1
941 1209
*
1
0
1
941 1477
#
1
1
0
697 1633
A
1
1
0
770 1633
B
1
1
1
852 1633
C
1
1
1
941 1633
D
0
0
0
0 = logic low, 1 = logic high
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
At this point the StGT output is activated and drives VC to VDD.
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
of the delayed steering flag by checking the appropriate bit in the
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal in-
terruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor perfor-
mance to meet a wide variety of system requirements.
Guard Time Adjustment: The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
tREC = tDP + tGTP
TID = tDA + tGTA
The value of tDP is a device parameter and tREC is the minimum
signal duration to be recognized by the receiver. A value for C1
of 0.1 µF is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be necessary to
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time ad-
justment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing tREC improves
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short tREC with a long
tDO would be appropriate for extremely noisy environments
where fast acquisition time and immunity to tone dropouts are
required. Design information for guard time adjustment is shown
in Figure 6.
Figure 5 Basic Steering Circuit
The contents of the output latch are updated on an active de-
layed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
Figure 6 Guard Time Adjustment
Call Progress Filter
A call progress (CP) mode can be selected, allowing the detec-
tion of various tones that identify the progress of a telephone call
on the network. The call progress tone input and DTMF input are
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
40-406-00012, Rev. G
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