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M-8888-01 Datasheet PDF Download - Clare Inc.

Номер произв M-8888-01
Описание DTMF Transceiver
Производители Clare Inc.
логотип Clare  Inc. логотип 
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M-8888-01 Даташит, Описание, Даташиты
Features
· Advanced CMOS technology for low power con-
sumption and increased noise immunity
· Complete DTMF transmitter/receiver in a single
chip
Standard 8051, 8086/8 microprocessor port
· Central office quality and performance
· Adjustable guard time
· Automatic tone burst mode
· Call progress mode
· Single +5 Volt power supply
· 20-pin DIP and SOIC packages
· 2 MHz microprocessor port operation
·· Inexpensive 3.58 MHz crystal
Applications
Paging systems
· Repeater systems/mobile radio
· Interconnect dialers
· PBX systems
· Computer systems
· Fax machines
· Pay telephone
·· Credit card verification
M-8888
DTMF Transceiver
Description
The M-8888 is a complete DTMF Transmitter
Receiver that features adjustable guard time, auto-
matic tone burst mode, call progress mode, and a fully
compatible 8051, 8086/8 microprocessor interface.
The receiver portion is based on the industry standard
M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for low-
distortion, highly accurate DTMF signaling. Tone
bursts can be transmitted with precise timing by mak-
ing use of the automatic tone burst mode. To analyze
call progress tones, a call progress filter can be select-
ed by an external microprocessor.
Ordering Information
Part #
Description
M-8888-01P
20-pin plastic DIP
M-8888-01SM 20-pin plastic SOIC
M-8888-01T
20-pin plastic SOIC,Tape and Reel
Pin Connections
Block Diagram
DS-M8888-R1
www.clare.com
1
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M-8888-01 Даташит, Описание, Даташиты
M-8888
Single-Ended Input Configuration
Differential Input Configuration
Functional Description
M-8888 functions consist of a high-performance
DTMF receiver with an internal gain setting amplifier
and a DTMF generator that contains a tone burst
counter for generating precise tone bursts and paus-
es. The call progress mode, when selected, allows the
detection of call progress tones. A standard 8051,
8086/8 series microprocessor interface allows access
to an internal status register, two control registers, and
two data registers.
ing the amplifier inputs at VDD/2. Provisions are made
for the connection of a feedback resistor to the op-amp
output (GS) for gain adjustment. In a single-ended
configuration, the input pins should be connected as
shown in the Single-Ended Input Configuration above.
Differential Input Configuration above shows the nec-
essary connections for a differential input configura-
tion.
Input Configuration
The input arrangement consists of a differential input
operational amplifier and bias sources (VREF) for bias-
Receiver Section
The low and high group tones are separated by apply-
ing the DTMF signal to the inputs of two sixth-order
Pin Functions
Name
IN+
IN-
GS
VREF
VSS
OSC1
OSC2
TONE
WR
CS
RS0
RD
IRQ /CP
D0-D3
ESt
St/GT
VDD
Description
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail.
Negative power supply input.
DTMF clock/oscillator input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible.
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Internal Register Functions on page 7. TTL compatible.
Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible..
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and
interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the
input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on
page 11.
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition).
Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register
the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply input.
2
www.clare.com
Rev. 1
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M-8888-01 Даташит, Описание, Даташиты
M-8888
switched capacitor bandpass filters with bandwidths
that correspond to the low and high group frequencies
listed in the Tone Encoding/Decoding below. The low
group filter incorporates notches at 350 and 440 Hz,
providing excellent dial tone rejection. Each filter out-
put is followed by a single-order switched capacitor fil-
ter that smoothes the signals prior to limiting. Limiting
is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals.
The comparator outputs provide full-rail logic swings
at the incoming DTMF signal frequencies.
A decoder employs digital counting techniques to
determine the frequencies of the incoming tones, and
to verify that they correspond to standard DTMF fre-
quencies. A complex averaging algorithm protects
against tone simulation by extraneous signals (such
as voice), while tolerating small deviations in frequen-
cy. The algorithm provides an optimum combination of
immunity to talkoff with tolerance to interfering fre-
quencies (third tones) and noise. When the detector
recognizes the presence of two valid tones (referred to
as signal condition), the early steering (ESt) output
goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Tone Encoding/Decoding
FLOW
697
FHIGH Digit
1209 1
697 1336 2
697 1477 3
770 1209 4
770 1336 5
770 1477 6
852 1209 7
852 1336 8
852 1477 9
941 1336 0
941 1209 *
941 1477 #
697 1633 A
770 1633 B
852 1633 C
941 1633 D
0 = logic low, 1 = logic high
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2 D1
00
01
01
10
10
11
11
00
00
01
01
10
10
11
11
00
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Basic Steering Circuit
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see the Basic Steering Circuit
above) to rise as the capacitor discharges. Provided
that the signal condition is maintained (ESt remains
high) for the validation period (tGTP), VC reaches the
threshold (VTSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see
the Tone Encoding/Decoding on left) into the receive
data register.
At this point the StGT output is activated and drives VC
to VDD. StGT continues to drive high as long as ESt
remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag
goes high, signaling that a received tone pair has
been registered. It is possible to monitor the status of
the delayed steering flag by checking the appropriate
bit in the status register. If interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is pre-
sented to the 4-bit bidirectional data bus when the
receive data register is read. The steering circuit works
in reverse to validate the interdigit pause between sig-
nals. Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal inter-
ruptions (dropout) too short to be considered a valid
pause. This capability, together with the ability to
select the steering time constants externally, allows
the designer to tailor performance to meet a wide vari-
ety of system requirements.
Steering Circuit:
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed
Guard Time Adjustment: The simple steering circuit
shown in the Basic Steering Circuit above is adequate
for most applications. Component values are chosen
according to the formula:
tREC = tDP + tGTP
TID = tDA + tGTA
Rev. 1 www.clare.com
3
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