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M-982-02P - Clare Inc. - Precise Call Progress Tone Detector

Номер произв M-982-02P
Описание Precise Call Progress Tone Detector
Производители Clare Inc.
логотип Clare  Inc. логотип 
предварительный просмотр
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M-982-02P Даташит, Описание, Даташиты
Features
Precise detection of call progress tones
Linear (analog) input
Digital (CMOS compatible), tri-state outputs
22-pin DIP and 20-pin SOIC
Single supply 3 to 5 volt (low power CMOS)
Inexpensive 3.58 MHz crystal time base
Wide dynamic range (30 dB)
Lower power consumption (power-down mode)
425 Hz detection
Applications
Automatic dialers
Dialing modems
Traffic
Measurement equipment
Test equipment
Service evaluation
Billing systems
Pin Diagram
M-982-02
Precise Call Progress Tone Detector
Description
The M-982-02 is an integrated circuit precise tone
detector for special-purpose use in automatic following
of switched telephone calls. The circuit uses low-
power CMOS techniques to provide the complete fil-
tering and control required for this function. The basic
timing of the M-982-02 is designed to permit operation
with almost any progress tone system.The use of inte-
grated circuit techniques allows the M-982-02 to pack
the five filters for call progress following into a single
22-pin DIP or 20-pin SOIC. A 3.58 MHz crystal-con-
trolled time base guarantees accuracy and repeatabil-
ity.
The M-982-02 is an enhanced drop-in replacement for
the M-982-01. It has a wider operating voltage range
(down to 3V). It has lower power consumption under
normal operating conditions. In addition, a power-
down (PD) feature is provided to further reduce power
consumption when inactive. It includes a 425 Hz
detector to support common international call progress
requirement.
Ordering Information
Part #
Description
M-982-02P
M-982-02S
M-982-02T
22-pin plastic DIP
20-pin plastic SOIC
20-pin plastic SOIC,Tape and Reel
Block Diagram
DS-M982-02-R4
www.clare.com
1
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M-982-02P Даташит, Описание, Даташиты
M-982-02
Absolute Maximum Ratings
Storage Temperature
-40 to 150°C
Operating Ambient Temperature
-40 to 85°C
VDD
Input Voltage on SIGIN
Input Voltages (except SIGIN)
Lead Soldering Temperature
7V
VSS - 6.5 to VDD + 0.3V
VSS - 0.3 to VDD + 0.3 V
260° C for 5 seconds
Note: Exceeding these ratings may permanently damage the M-982-02.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Specifications
Operating
Conditions
Power
VREF
Signal
Detection
Parameter
VDD
Power supply noise
Current drain (IDD)
VREF
Impedance
Frequency range
Level: VDD = 5.0V
Conditions
-
0.1 - 5 kHz
VREF open
-
-
in-band signal
XRANGE = open
XRANGE = VSS
Signal
Rejection
Outputs
Inputs
Level: VDD = 3.0V
Duration (tDD)
Bridge time (tBB)
Level skew between adjacent
XRANGE = open
XRANGE = VSS
-
-
inband signals
for detection of both
High level to low level signal for
high = 0 dBm (775 mV)
detection of both (tIL)
Time to output (tDO)
low = -30 dBm (24.5 mV)
SIGIN -24 dBm
SIGIN < -24 dBm
Time from DET n to STROBE (tDS)
Frequency range
-
-
Level: VDD = 5.0V
Level: VDD = 3.0V
Interval duration (tID)
Time to output (TIO)
DET n,
STROBE pins
DET n pins
EN, OE, XRANGE,
VOL
VOH
IOZ
VIL
XRANGE = open
XRANGE = VSS
XRANGE= open
XRANGE = VSS
-
-
ISINK = -1mA
ISOURCE=1mA
VO=VDD, VSS
-
MODE, PD pins
VIH
VDD = 5V
VDD = 2.7V
Pull-up and Pull-down MODE = VSS
VDD = 5V
currents
VDD = 2.7V
/Xrange = VSS
-
PD =VDD
-
Min
2.7
-
-
48% of VDD
3.25
-1
-30
(24.5 mV)
-40
(7.8 mV)
-33 (17.4 mV)
-43 (5.5 mV)
200
-
-
1
-
-
-
-6
-
-
-
-
160
-
-
VDD -0.5
-
-
VDD - 2.0
VDD - 0.5
12.5
4
2
4
Max
5.5
20
15
52% of VDD
8.25
+1
0
(775 mV)
-10
(245 mV)
-3 (549 mV)
-13 (173.5 mV)
-
20
Units
V
mV p-p
mA
V
kW
% of fo
dBm
dBm
-
dBm
dBm
ms
ms
Notes
-
-
-
1
6 dB
- s-
200
240
10
-6
-50(2.5 mV)
-60 (0.8 mV)
-53 (1.7 mV)
-63 (.6 mV)
-
200
0.5
-
1
0.5
-
-
50
20
6
10
ms
ms
ms
% of fo
dBm
dBm
dBm
dBm
ms
ms
V
V
µA
V
V
V
µA
µA
µA
µA
-
1
-
-
2
www.clare.com
Rev. 4
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M-982-02P Даташит, Описание, Даташиты
M-982-02
Specifications (continued)
Parameter
Conditions
Clock
Tri-state
Operation
SIGIN pin
Voltage range
Input impedance
Input spectrum
External clock
connected to XIN pin
VIL
VIH
Duty cycle
XIN, XOUT with crystal Capacitance
osc. active
Internal resistance
Power up (TPU)
X358 pin
VOL
VOH
tEN,(High Z to Low Z)
tDE,(Low Z to High )Z
Duty cycle
CL = 50 pF,
RL = 100 kW
-
f=500 Hz
-
XOUT open
XOUT open
XOUT open
-
-
PD hi to lo
CL = 20 pF,
ISINK = -1mA
CL = 20 pF,
ISOURCE =1mA
CL = 20 pF
-
-
Unless otherwise noted, VDD - VSS = 5V, Ta = 25°C, PD at logical low state, and XRANGE at a logical high state.
Power levels are in dBm referenced to 600 ohm.
Notes:
DC voltages are referenced to VSS.
1. Per tone.
Min
-6.5
80
-
-
VDD-0.2
40
-
20
-
-
VDD - 0.2
40
250
250
Max Units Notes
VDD V
- k
28 kHz
0.2 V
-V
60 %
10 pF
- MW
30 ms
0.2 V
-V
60 %
ns
ns
Pin Functions
Pin
DET 1
DET 2
DET 3
DET 4
DET 5
EN
OE
SIGIN
STROBE
VDD
VREF
VSS
X358
XIN
XOUT
XRANGE
MODE
PD
Funtion
Active high tri-state output, detect for 350 Hz.
Active high tir-state ooutput, detect for 400/620 Hz.
(See Note.)
Active high tri-state output, detect for 440 Hz.
Active high tri-state output, detect for 480 Hz.
Active high tri-state output, detect for 425 Hz.
Active high enabled, when low drives STROBE low.
Active high input. When low tri-state DET n pins.
Analog signal input (internally capacitive coupled).
Active high output, indicates valid DET n.
Most positive power supply input pin.
Internally generated mid-power supply voltage
(output).
Most negative power supply input pin.
Buffered oscillator output (3.58 MHz).
Crystal oscillator or digital clock input.
Crystal oscillator output. Used only with a crystal.
Use X358 when clock output signal is required.
Active low input. Adds 10 dB of gain to input stage.
Compatibility selection. Connection to VSS selects
400 Hz detection. (M-981-02 emulation.) Connection
to VDD or no connection selects 620 Hz detection.
Power-down operation, logic high inhibits internal
clock. Internal pulldown resistor.
Note: This output indicates 400 Hz detect when MODE is connected to VSS and 620
Hz detect when open, or connected to VDD.
Call Progress Tones
Frequency (HZ)
12
350 440
400 Off
440 Off
440 480
440 620
480 Off
480 620
350 Off
620 Off
941 1209
425 Off
Use
Dial Tone
Special
Alert Tone
Audible Ring
Pre-empt
Bell High Tone
Reorder (Bell Low)
Special
Special
*DTMF “ ”
European
Rev. 4 www.clare.com
3
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