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PDF NJU72014 Data sheet ( Hoja de datos )

Número de pieza NJU72014
Descripción 2Vrms Ground Referenced Stereo Line Amplifier
Fabricantes New Japan Radio 
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NJU72014
2Vrms Ground Referenced Stereo Line Amplifier with LPF
Q GENERAL DESCRIPTION
The NJU72014 is an audio line Amplifier . It can swing 2Vrms
(5.6V peak-to-peak) signal at 3.3V operating voltage.
Ground-referenced outputs eliminate output coupling capacitor.
The pop noise suppression circuit removes a pop noise at the
power-on and power-off.
It is suitable for audio line interface of audio equipment which
does not have over 9V regulator.
Q PACKAGE OUTLINE
NJU72014RB2
Q APPLICATIONS
O Audio applications requiring 2Vrms outputs
Q FEATURES
O Operating Voltage
+2.7 to +3.6V
O Operating Current
IDD=4.5mA typ.at V+=3.3V, RL=47k, No Signal
O Output Coupling Capacitor-less
O Pop Noise Suppression Circuit
O 2nd order LPF
O C-MOS Technology
O Package Outline
MSOP10 (TVSP10)
Q BLOCK DIAGRAM
Q PIN CONFIGURATION
OUTL
V+
1 10
OUTR
INL INR
MUTE
Bias
Pop Noise
Suppression
Charge Pump
V-
GND CP CM
56
No. Symbol
1 INL
2 OUTL
3 V+
4 CP
5 CN
6 V-
7 MUTE
8 GND
9 OUTR
10 INR
Function
Lch Input
Lch Output
V+ Power Supply
Flying Capacitor Positive Terminal
Flying Capacitor Negative Terminal
V- Power Supply
Mute / Pop Noise Suppression
Ground
Rch Output
Rch Input
Ver.1.9E
–1–

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NJU72014 pdf
NJU72014
1.1 External parts
1.1.1 Input coupling capacitors Ci (C2, C8)
The input coupling capacitor (Ci) and the total of the external resistance (R1, R3) and the input
resistance (Rin=218ktyp.) for the non-inverted terminal form a high-pass filter with the corner
frequency determined in [fc=1/(2π x (R1+218kΩ) x Ci)). It is necessary to adjust 1uF or more.
1.1.2 Flying capacitor (C4)
Use capacitors with a low-ESR (ex. ceramic capacitors) for optimum performance. Design to provide
low impedance for the wiring between CP terminal (4pin), CN terminal (5pin), and the flying capacitor
(C4).
C4=1uF
CP(4pin)
CN(5pin)
Fig.2 The NJU72014 block diagram (4pin, 5pin)
1.1.3 Hold capacitor (C6)
Use capacitors with a low-ESR (ex. ceramic capacitors) for optimum performance. Design to provide
low impedance for the wiring between the hold capacitor (C6), V- terminal (6pin) and the GND on the
PCB.
Separate the GND pattern connecting to the hold capacitor (C6) from that connecting to the GND
terminal (8pin), thus suppressing the influence of switching noise by removing the common impedance
of the GND wiring.
Design no short-circuits of V- terminal (6pin) and V+ terminal (3pin) on the PCB pattern.
V-(6pin)
GND(8pin)
C6
Fig.3 The NJU72014 block diagram (6pin, 8pin)
–5–

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