|
|
PDF WM8904 Data sheet ( Hoja de datos )
| Número de pieza | WM8904 | |
| Descripción | Ultra Low Power CODEC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de WM8904 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
w
WM8904
Ultra Low Power CODEC for Portable Audio Applications
DESCRIPTION
The WM8904 is a high performance ultra-low power stereo
CODEC optimised for portable audio applications.
The device features stereo ground-referenced headphone
amplifiers using the Wolfson ‘Class-W’ amplifier techniques -
incorporating an innovative dual-mode charge pump
architecture - to optimise efficiency and power consumption
during playback. The ground-referenced headphone and line
outputs eliminate AC coupling capacitors, and both outputs
include common mode feedback paths to reject ground
noise.
Control sequences for audio path setup can be pre-loaded
and executed by an integrated control write sequencer to
reduce software driver development and minimise pops and
clicks via Wolfson’s SilentSwitch™ technology.
The analogue input stage can be configured for single
ended or differential inputs. Up to 3 stereo microphone or
line inputs may be connected. The input impedance is
constant with PGA gain setting.
A stereo digital microphone interface is provided, with a
choice of two inputs.
A dynamic range controller provides compression and level
control to support a wide range of portable recording
applications. Anti-clip and quick release features offer good
performance in the presence of loud impulsive noises.
ReTuneTM Mobile 5-band parametric equaliser with fully
programmable coefficients is integrated for optimization of
speaker characteristics. Programmable dynamic range
control is also available for maximizing loudness, protecting
speakers from clipping and preventing premature shutdown
due to battery droop.
Common audio sampling frequencies are supported from a
wide range of external clocks, either directly or generated
via the FLL.
The WM8904 can operate directly from a single 1.8V
switched supply. For optimal power consumption, the digital
core can be operated from a 1.0V supply.
FEATURES
3.0mW quiescent power consumption for DAC to
headphone playback
DAC SNR 96dB typical, THD -86dB typical
ADC SNR 91dB typical, THD -80dB typical
2.4mW quiescent power consumption for analogue bypass
playback
Control write sequencer for pop minimised start-up and
shutdown
Single register write for default start-up sequence
Integrated FLL provides all necessary clocks
- Self-clocking modes allow processor to sleep
- All standard sample rates from 8kHz to 96kHz
Stereo digital microphone input
3 single ended inputs per stereo channel
1 fully differential mic / line input per stereo channel
Digital Dynamic Range Controller (compressor / limiter)
Digital sidetone mixing
Ground-referenced headphone driver
Ground-referenced line outputs
32-pin QFN package (4 x 4mm, 0.4mm pitch)
36-ball WLCSP package (2.6 x 2.5mm, 6 x 6 ball grid,
0.4mm pitch)
APPLICATIONS
Portable multimedia players
Multimedia handsets
Handheld gaming
Wireless headsets
Mobile internet devices
Netbooks
WOLFSON MICROELECTRONICS plc
Pre-Production, July 2014, Rev 3.4
Copyright 2014 Wolfson Microelectronics plc
1 page  
Pre-Production
WM8904
AUDIO DATA FORMATS (NORMAL MODE) ................................................................................................................ 92
AUDIO DATA FORMATS (TDM MODE)........................................................................................................................ 95
DIGITAL AUDIO INTERFACE CONTROL...................................................................... 97
AUDIO INTERFACE OUTPUT TRI-STATE ................................................................................................................... 98
BCLK AND LRCLK CONTROL...................................................................................................................................... 98
COMPANDING .............................................................................................................................................................. 99
LOOPBACK ................................................................................................................................................................. 101
DIGITAL PULL-UP AND PULL-DOWN........................................................................................................................ 101
CLOCKING AND SAMPLE RATES .............................................................................. 102
SYSCLK CONTROL .................................................................................................................................................... 103
CONTROL INTERFACE CLOCKING .......................................................................................................................... 104
CLOCKING CONFIGURATION ................................................................................................................................... 104
ADC / DAC CLOCK CONTROL ................................................................................................................................... 105
OPCLK CONTROL ...................................................................................................................................................... 106
TOCLK CONTROL ...................................................................................................................................................... 106
ADC / DAC OPERATION AT 88.2K / 96K ................................................................................................................... 107
FREQUENCY LOCKED LOOP (FLL) ........................................................................... 108
FREE-RUNNING FLL CLOCK ..................................................................................................................................... 112
GPIO OUTPUTS FROM FLL ....................................................................................................................................... 113
EXAMPLE FLL CALCULATION................................................................................................................................... 113
EXAMPLE FLL SETTINGS.......................................................................................................................................... 114
GENERAL PURPOSE INPUT/OUTPUT (GPIO) .......................................................... 115
IRQ/GPIO1................................................................................................................................................................... 115
GPIO2 .......................................................................................................................................................................... 116
GPIO3 .......................................................................................................................................................................... 116
BCLK/GPIO4................................................................................................................................................................ 117
INTERRUPTS................................................................................................................ 118
USING IN1L AND IN1R AS INTERRUPT INPUTS...................................................................................................... 122
CONTROL INTERFACE................................................................................................ 123
CONTROL WRITE SEQUENCER ................................................................................ 125
INITIATING A SEQUENCE.......................................................................................................................................... 125
PROGRAMMING A SEQUENCE ................................................................................................................................ 126
DEFAULT SEQUENCES ............................................................................................................................................. 129
START-UP SEQUENCE.............................................................................................................................................. 129
SHUTDOWN SEQUENCE........................................................................................................................................... 131
POWER-ON RESET ..................................................................................................... 133
QUICK START-UP AND SHUTDOWN ......................................................................... 135
QUICK START-UP (DEFAULT SEQUENCE).............................................................................................................. 135
FAST START-UP FROM STANDBY ........................................................................................................................... 135
QUICK SHUTDOWN (DEFAULT SEQUENCE)........................................................................................................... 136
SOFTWARE RESET AND CHIP ID .............................................................................. 137
REGISTER MAP ................................................................................................ 138
REGISTER BITS BY ADDRESS................................................................................... 142
APPLICATIONS INFORMATION ...................................................................... 181
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 181
MIC DETECTION SEQUENCE USING MICBIAS CURRENT ..................................... 183
PACKAGE DIMENSIONS.................................................................................. 185
IMPORTANT NOTICE ....................................................................................... 187
ADDRESS ..................................................................................................................... 187
REVISION HISTORY ......................................................................................... 188
w
PP, Rev 3.4, July 2014
5
5 Page 
Pre-Production
WM8904
ELECTRICAL CHARACTERISTICS
TERMINOLOGY
1. Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output
noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ratio is also called idle channel noise.
(No Auto-zero or Automute function is employed).
2. Total Harmonic Distortion (dB) – THD is the difference in level between a 1kHz full scale sinewave output signal and
the first seven harmonics of the output signal. The amplitude of the fundamental frequency of the output signal is
compared to the RMS value of the next seven harmonics and expressed as a ratio.
3. Total Harmonic Distortion + Noise (dB) – THD+N is the difference in level between a 1kHz full scale sine wave output
signal and all noise and distortion products in the audio band. The amplitude of the fundamental reference frequency of
the output signal is compared to the RMS value of all other noise and distortion products and expressed as a ratio.
4. Channel Separation (dB) – is a measure of the coupling between left and right channels. A full scale signal is applied
to the left channel only, the right channel amplitude is measured. Then a full scale signal is applied to the right channel
only and the left channel amplitude is measured. The worst case channel separation is quoted as a ratio.
5. Multi-Path Crosstalk (dB) – is the measured signal level in the idle path at the test signal frequency relative to the
signal level at the output of the active path. The active path is configured and supplied with an appropriate input signal
to drive a full scale output, with signal measured at the output of the specified idle path.
6. Channel Level Matching (dB) – measures the difference in gain between the left and the right channels.
7. Power Supply Rejection Ratio (dB) – PSRR is a measure of ripple attenuation between the power supply pin and an
output path. With the signal path idle, a small signal sine wave is summed onto the power supply rail, The amplitude of
the sine wave is measured at the output port and expressed as a ratio.
8. All performance measurements carried out with 20kHz AES17 low pass filter for distortion measurements, and an
A-weighted filter for noise measurement. Failure to use such a filter will result in higher THD and lower SNR and
Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band
noise; although it is not audible it may affect dynamic specification values.
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
DCVDD = 1.0V
DBVDD = 1.8V
AVDD = CPVDD =1.8V
Ambient temperature = +25°C
Audio signal: 1kHz sine wave, sampled at 48kHz with 24-bit data resolution
SYSCLK_SRC = 0 (system clock comes direct from MCLK, not from FLL).
Additional, specific test conditions are given within the relevant sections below.
w
PP, Rev 3.4, July 2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8904.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| WM8903 | Ultra Low Power CODEC | Wolfson Microelectronics |
| WM8904 | Ultra Low Power CODEC | Wolfson Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |