CLC016 PDF даташит
Спецификация CLC016 изготовлена «National Semiconductor» и имеет функцию, называемую «Data Retiming PLL with Automatic Rate Selection». |
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Детали детали
Номер произв | CLC016 |
Описание | Data Retiming PLL with Automatic Rate Selection |
Производители | National Semiconductor |
логотип |
20 Pages
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July 1998
CLC016
Data Retiming PLL with Automatic Rate Selection
General Description
National’s Comlinear CLC016 is a low-cost, monolithic, data
retiming phase-locked loop (PLL) designed for high-speed
serial clock and data recovery. The CLC016 simplifies high-
speed data recovery in multi-rate systems by incorporating
auto-rate select (ARS) circuitry on chip. This function allows
the user to configure the CLC016 to recognize up to four dif-
ferent data rates and automatically adjust to provide accu-
rate, low-jitter clock and data recovery. A single resistor is
used to set each data rate anywhere between 40 Mbps and
400 Mbps. No potentiometers, crystals, or other external ICs
are required to set the rate.
The CLC016 has output jitter of only 130 pspp at a 270 Mbps
data rate and 0.25% fractional loop bandwidth. Low phase
detector output offset and low VCO injection combine to en-
sure that the CLC016 does not generate bit errors or large
phase transients in response to extreme fluctuations in data
transition density. The result is improved performance when
handling the pathological patterns inherent in the SMPTE
259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop fil-
ter allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V
or −5.2V power supplies. The serial data inputs and outputs,
as well as the recovered clock outputs, allow single- or
differential-ECL interfacing. The logic control inputs are TTL-
compatible.
Features
n Retimed data output
n Recovered clock output
n Auto and manual rate select modes
n Four user-configurable data rates
n No potentiometers required
n External loop bandwidth control
n Frequency detector for lock acquisition
n Carrier detect output
n Output MUTE function
n Single supply operation: +5V or −5.2V
n Low cost
Key Specifications
n Low jitter: 130 pspp @ 270 Mbps, 0.25% fractional loop
bandwidth (0.675 MHz)
n High data rates: 40 Mbps − 400 Mbps
n Low supply current: 100 mA, including output biasing
n Flexible fractional loop bandwidth: from 0.05% to 0.5%
Applications
n SMPTE 259M serial digital interfaces: NTSC/PAL, 4:2:2
component, 360 Mbps wide screen
n Serial digital video routing and distribution
n Clock and data recovery for high-speed data
transmission
n Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
DS100087-1
Order Number
CLC016ACQ
CLC016AJQ
Temperature
0˚C to +70˚C
–40˚C to +85˚C
Package
PLCC V28A
PLCC V28A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100087
www.national.com
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Typical Application
Four-Rate Clock and Data Recovery with Automatic Rate Selection
Pinout
DS100087-2
www.national.com
28-pin PLCC
DS100087-3
2
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC–VEE)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering 4 sec)
ESD Rating (Note 12)
Package Thermal Resistance
θJA 28-Pin PLCC
θJC 28-Pin PLCC
−0.3, +6.0V
+150˚C
−65˚C to +150˚C
+260˚C
2kV
85˚C/W
35˚C/W
Reliability Information
MTTF (based on limited life
test data)
2.6 x 107 hours
Recommended Operating
Conditions
Supply Voltage (VCC–VEE)
Operating Temperature
Jitter Transfer Function Fractional Loop
Bandwidth
SCO/SCO, SDO/SDO Minimum
Voltage (Note 13)
4.5V to 5.5V
–40˚C to +85˚C
0.05% to 0.5%
VCC – 1.6V
Electrical Characteristics
(VCC = 0V, VEE = −5V, RBW = 500Ω; CZ = 0.1 µF; CP = 82 pF; Rn = 3504, CARS = 0.1 µF; unless specified).
Parameter
Conditions
Typ
+25˚C
Min/Max
+25˚C
Min/Max
Full Temp.
Range
DYNAMIC PERFORMANCE
Residual Jitter
270 Mbps PRN sequence 150 250
(Notes 3, 4)
300
Acquisition Time
270 Mbps PRN sequence
6 x 105
Minimum Average Data Rate, fCLK
Full Temperature Range
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Note 3)
100 100
0 to 70˚
Maximum Average Data Rate, fCLK
4.5V ≤ (VCC − VEE) ≤ 5.5V
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Note 3)
40
400
400
Tracking and Capture Range
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Notes 3, 5)
±8.3
±5.0/
±13.0
±2.5/
±18.0
VCO Power Supply Sensitivity
(Note 3)
±0.8
±1.2
±1.3
VCO Temperature Sensitivity
±250
Jitter Transfer Function −3 dB bandwidth
(Fractional Loop Bandwidth), λBW
Jitter Transfer Function Peaking
RBW = 100Ω (Notes 6, 7)
RBW = 500Ω (Notes 6, 7)
RBW = 1000Ω (Notes 6, 7)
RBW = 500Ω, 270 Mbps
(Note 6)
0.05
0.25
0.5
<0.1
STATIC PERFORMANCE
Power Supply Current, IEE
Voltage on Selected Rn Resistor
Voltage on Unselected Rn Resistor
VC/VC Common-Mode Voltage, VCM
VC/VC Diff-Mode Voltage Range, VDM
DDI/DDI
Input Range Upper Limit, VH
Input Range Lower Limit, VL
Minimum Differential Input Amplitude, V∆
Input Current
(Note 3)
(Note 8)
(Note 8)
(Note 8)
(Note 8)
(Note 3)
105
VCC −2.2
VCC
VCC −1.5
±300
125
VCC
VEE +2.5
200
36
133
200
6
SCO/SCO, SDO/SDO
Output Current, IOUT
Output Voltage Swing, VOUT
ACQ/WR, MUTE, RDO/RD1
Voltage Input — LOW, VIL
Voltage Input — HIGH, VIH
Input Current (IIN)
(Note 3)
Rcollector = 75Ω (Note 3)
(Note 9)
(Note 3)
(Note 3)
11
9.3/12
8.6/12.7
725 625/900
VEE + 0.8
VEE + 2.0
±100
VEE + 0.8
VEE + 2.0
±500
Units
pspp
bit cells
Mbps
Mbps
Mbps
%fCLK
%V
ppm/˚C
%fCLK
%fCLK
%fCLK
dB
mA
V
V
V
mV
V
V
mV
µA
mA
mV
V
V
nA
3 www.national.com
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