CLC018AJVJQ PDF даташит
Спецификация CLC018AJVJQ изготовлена «National Semiconductor» и имеет функцию, называемую «8 x 8 Digital Crosspoint Switch/ 1.4 Gbps». |
|
Детали детали
Номер произв | CLC018AJVJQ |
Описание | 8 x 8 Digital Crosspoint Switch/ 1.4 Gbps |
Производители | National Semiconductor |
логотип |
18 Pages
No Preview Available ! |
October 1998
CLC018
8 x 8 Digital Crosspoint Switch, 1.4 Gbps
General Description
National’s Comlinear CLC018 is a fully differential 8x8 digital
crosspoint switch capable of operating at data rates exceed-
ing 1.4 Gbps per channel. Its non-blocking architecture uti-
lizes eight independent 8:1 multiplexers to allow each output
to be independently connected to any input and any input to
be connected to any or all outputs. Additionally, each output
can be individually disabled and set to a high-impedance
state. This TRI-STATE® feature allows flexible expansion to
larger switch array sizes.
Low channel-to-channel crosstalk allows the CLC018 to pro-
vide superior all-hostile jitter of 50 psPP. This excellent signal
fidelity along with low power consumption of 850 mW make
the CLC018 ideal for digital video switching plus a variety of
data communication and telecommunication applications.
The fully differential signal path provides excellent noise im-
munity, and the I/Os support ECL and PECL logic levels. In
addition, the inputs may be driven single-ended or differen-
tially and accept a wide range of common mode levels in-
cluding the positive supply. Single +5V or −5V supplies or
dual +5V supplies are supported. Dual supply mode allows
the control signals to be referenced to the positive supply
(+5V) while the high-speed I/O remains ECL compatible.
The double row latch architecture utilized in the CLC018 al-
lows switch reprogramming to occur in the background dur-
ing operation. Activation of the new configuration occurs with
a single “configure” pulse. Data integrity and jitter perfor-
mance on unchanged outputs are maintained during recon-
figuration. Two reset modes are provided. Broadcast reset
results in all outputs being connected to input port DI0.
TRI-STATE Reset results in all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS
process and is available in a 64-lead plastic quad flat pack
(PQFP).
Features
n Fully differential signal path
n Non-Blocking
n Flexible expansion to larger array sizes with very low
power
n Single +5/−5V or dual ±5V operation
n TRI-STATE outputs
n Double row latch architecture
n 64-lead PQFP package
Applications
n Serial digital video routing (SMPTE 259M)
n Telecom/datacom switching
n ATM SONET
Key Specifications
n High speed: >1.4 Gbps
n Low jitter:
<50 psPP for rates <500 Mbps
<100 psPP for rates <1.4 Gbps
n Low power; 850 mW with all outputs active
n Fast output edge speeds: 250 ps
CLC018 Block Diagram
© 1998 National Semiconductor Corporation DS100088
DS100088-2
DS100088-1
www.national.com
No Preview Available ! |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC–VEE)
VLL Maximum
VLL Minimum
Storage Temperature Range
Lead Temp. (Soldering 4 sec.)
ESD Rating
Package Thermal Resistance
θJA 64-Pin PQFP
−0.3V to +6.0V
VCC +6V
VCC −0.5V
−65˚C to +150˚C
+260˚C
TBD
75˚C/W
θJC 64-Pin PQFP
Reliability Information
Transistor Count
MTTF (based on limited life test data)
15˚C/W
3000
TBD
Recommended Operating
Conditions
Supply Voltage (VCC–VEE)
Operating Temperature
VLL
4.5V to 5.5V
−40˚C to +85˚C
VCC or VCC +5V
Electrical Characteristics
(VCC = 0V, VEE = −5V, VLL = 0V; unless otherwise specified) (Note 4).
Parameter
Conditions
DYNAMIC PERFORMANCE
Max. Data Rate/Channel (NRZ)
Channel Jitter
Propagation Delay (input to output)
Propagation Delay Match
Output Rise/Fall Time
Duty Cycle Distortion
CONTROL TIMING: CONFIGURATION
OA Bus to LOAD ↑ Setup Time (T1)
LOAD ↓ to OA Bus Hold Time (T2)
IA Bus, TRI to LOAD ↓ Setup Time (T3)
LOAD ↓ to IA Bus, TRI Hold Time (T4)
Min Pulse Width: (T5)
LOAD
CNFG
LOAD ↑ to CNFG ↑ Delay (T6)
CNFG ↑ to Valid Delay (T7)
CNFG ↑ to Output TRI-STATE Delay (T8)
CNFG ↑ to Output Active Delay (T9)
CONTROL TIMING: RESET (Note 11)
TRI to RES ↑ Setup Time (T10)
RES ↓ to TRI Hold Time (T11)
Min Pulse Width: RES (T12)
RES ↑ to TRI-STATE Mode Delay (T13)
RES ↑ to Broadcast Mode Delay (T14)
STATIC PERFORMANCE
Signal I/O:
Min Input Swing, Differential
Input Voltage Range Lower Limit
Input Voltage Range Upper Limit
Input Bias Current
Output Current
(Note 5)
Data Rate <500 Mbps
(Note 6)
Data Rate <1.4 Gbps
(Note 6)
(Note 7)
(Note 8)
(Note 9)
(Note 3)
(Notes 3, 12)
(Note 3)
Typ
+25˚C
1.4
50
100
0.75
±200
250
10
15
0
5
5
10
10
0
20
20
70
5
5
10
20
70
Min/Max
+25˚C
Min/Max
−40˚C to
+85˚C
Units
Gbps
psPP
psPP
ns
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
−2
0.4
1.5
10.7
200
0.4/3.1
8.53/12.80
200
0.3/3.8
7.20/14.3
mVPP
V
V
µA/output
mA
www.national.com
2
No Preview Available ! |
Electrical Characteristics (Continued)
(VCC = 0V, VEE = −5V, VLL = 0V; unless otherwise specified) (Note 4).
Parameter
Conditions
Signal I/O:
Output Voltage Swing
Output Voltage Range Lower Limit
Output Voltage Range Upper Limit
Control Inputs:
Input Voltage - HIGH VIH min
Input Voltage - LOW VIL max
Input Voltage - HIGH VIH min
Input Voltage - LOW VIL max
Input Current - HIGH
Input Current - LOW
MISCELLANEOUS PERFORMANCE
VCC Supply Current
VCC Supply Current
VLL Supply Current
VLL Supply Current
Input Capacitance
Output Capacitance
RLOAD = 75Ω
(Note 3)
(Note 3)
VLL = +5V (Note 3)
VLL = +5V (Note 3)
VIH = VLL (Note 3)
VIL = VLL −5V (Note 3)
All Outputs Active
(Notes 3, 13, 14)
All Outputs TRI-STATE
(Note 3)
VLL = 0V (Note 3)
VLL = +5V (Note 3)
Typ
+25˚C
800
−2.5
0
−1
−4
4
1
1
−100
Min/Max
+25˚C
Min/Max
−40˚C to
+85˚C
Units
640/960 540/1060
mV
V
V
−0.5
−4.5
4.5
0.5
0.2/2.0
−200/10
−0.5
−4.5
4.5
0.5
0.1/2.5
−250/15
V
V
V
V
µA
µA
157
127/202 119/217
mA
7
3/11
2/12
mA
2.5
1.7/3.3
1.5/3.5
mA
7 mA
1.5 pF
2 pF
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level spec. is 100% tested at +25˚C.
Note 4: VLL and all VEE supply pins are bypassed with 0.01 µF ceramic capacitor.
Note 5: Bit error rate less than 10−9 over 50% of the bit cell interval.
Note 6: Measured using a pseudo-random (223−1 pattern) binary sequence with all other channels active with an uncorrelated signal.
Note 7: Spread in propagation delays for all input/output combinations.
Note 8: Measured between the 20% and 80% levels of the waveform.
Note 9: Difference in propagation delay for output low-to-high vs. output high-to-low transition.
Note 10: Refer to the Configuration Timing Diagram.
Note 11: Refer to the Reset Timing Diagram.
Note 12: The bias current for high speed data input depends on the number of data outputs that are selecting that input.
Note 13: The VCC supply current is a function of the number of active data outputs. IVCC 18*N + 7 mA where N is an integer from 0 to 8.
Note 14: IVEE = IVCC + IVLL.
3 www.national.com
Скачать PDF:
[ CLC018AJVJQ.PDF Даташит ]
Номер в каталоге | Описание | Производители |
CLC018AJVJQ | 8 x 8 Digital Crosspoint Switch/ 1.4 Gbps | National Semiconductor |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |