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CLC109AJP PDF даташит

Спецификация CLC109AJP изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Low-Power/ Wideband/ Closed-Loop Buffer».

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Номер произв CLC109AJP
Описание Low-Power/ Wideband/ Closed-Loop Buffer
Производители National Semiconductor
логотип National Semiconductor логотип 

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CLC109AJP Даташит, Описание, Даташиты
N
CLC109
Low-Power, Wideband, Closed-Loop Buffer
June 1999
General Description
The CLC109 is a high-performance, closed-loop monolithic buffer
intended for power sensitive applications. Requiring only 35mW of
quiescent power (±5V supplies), the CLC109 offers a high bandwidth
of 270MHz (0.5Vpp) and a slew rate of 350V/µs. Even with this
minimal dissipation, the CLC109 can easily drive a demanding
100load. The buffer specifications are for a 100load.
With its patented closed-loop topology, the CLC109 has significant
performance advantages over conventional open-loop designs.
Applications requiring low (2.8Ω) output impedance and nearly
ideal unity gain (0.997) through very high frequencies will benefit
from the CLC109's superior performance. Power sensitive
applications will benefit from the CLC109's excellent performance
on reduced or single supply voltages.
Features
s High small-signal bandwidth (270MHz)
s Low supply current (3.5mA @ ±5V)
s Low output impedance (2.8)
s 350V/µs slew rate
s Single supply operation (0 to 3V supply min.)
s Evaluation boards and Spice models
Applications
s Video switch buffers
s Test point drivers
s Low power active filters
s DC clamping buffer
s High-speed S & H circuits
s Inverting op amp input buffer
Constructed using an advanced, complementary bipolar process
and Comlinear's proven high-performance architectures, the
CLC109 is available in several versions to meet a variety of
requirements.
CLC109AJP -40°C to +85°C 8-pin Plastic DIP
CLC109AJE -40°C to +85°C 8-pin Plastic SOIC
CLC109ALC -40°C to +85°C dice
CLC109AMC -55°C to +125°C dice qualified to Method 5008,
MIL-STD-883, Level B
CLC109AJM5 -40°C to +85°C 5-pin SOT
Contact factory for other packages and DESC SMD number.
Vo
PINOUT
SOT23-5
VEE
Vnon-inv
VCC
PINOUT
DIP & SOIC
Vinv
Typical Application
CLC109
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Single-Supply Circuit
http://www.national.com









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CLC109AJP Даташит, Описание, Даташиты
CLC109 EleCcLtrCic1a0l9CEhleacrtarcictaelrCishtaicrasc(t±eVrCCis=t±ic5sV, RL= V10c0c=un±le5sVs ,spRecLif=ied1) 00)
PARAMETER
CONDITIONS
TYP
MIN/MAX RATINGS
UNITS SYMBOL
Ambient Temperature CLC109AJ
+25°C -40°C +25°C +85°C
FREQUENCY RESPONSE
small signal bandwidth
gain flatness
flatness
peaking
rolloff
differential gain
differential phase
Vout < 0.5Vpp
Vout < 2.0Vpp
Vout < 0.5Vpp
DC-30MHz
DC-200MHz
DC-60MHz
4.43MHz, 150load
4.43MHz, 150load
270
120
0
0
0.1
0.7
0.03
200
90
±0.1
1.0
0.4
1.5
0.05
200 150
90 70
±0.1 ±0.1
0.3 0.3
0.4 0.6
1.0 1.0
0.05 0.1
MHz
MHz
dB
dB
dB
%
°
SSBW
LSBW
GFL
GFPH
GFRH
DG
DP
TIME DOMAIN RESPONSE
rise and fall time
settling time to ±0.05%
overshoot
slew rate
0.5V step
2.0V step
2.0V step
0.5V step
4V step
1.3 1.7
4.4 6
12 25
3 15
350 220
1.7 2.3
67
18 25
10 10
250 220
ns
ns
ns
%
V/µsec
TRS
TRL
TS
OS1
SR
DISTORTION AND NOISE PERFORMANCE
2nd harmonic distortion
3rd harmonic distortion
equivalent output noise
2Vpp, 20MHz
2Vpp, 20MHz
voltage
current
-46 -36
-55 -50
3.3 4.1
1.3 3
-38 -38
-50 -45
4.1 4.5
22
dBc
dBc
nV/Hz
pA/Hz
HD2
HD3
VN
ICN
STATIC DC PERFORMANCE
small signal gain
no load
100load
output resistance
DC
*output offset voltage
average temperature coefficient
* input bias current
average temperature coefficient
power supply rejection ratio
* supply current
no load
0.997
0.96
2.8
1
±10
±2
±30
-56
3.5
0.995
0.94
5.0
±8.2
±40
±8
±50
-48
4
0.995
0.95
4.0
±5
±4
-48
4
0.994
0.95
4.0
±6
±30
±4
±25
-46
4
V/V
V/V
mV
µV/°C
µA
nA/°C
dB
mA
GA1
GA2
RO
VIO
DVIO
IBN
DIBN
PSRR
ICC
MISCELLANEOUS PERFORMANCE
integral endpoint linearity
±1V, full scale
input resistance
input capacitance
CERDIP
Plastic DIP
output voltage range
no load
RL=100
RL=100, 0°C
output current
0°C
0.5
1.5
2.5
1.25
4.0
+3.8,-2.5
+60,-30
1.0 0.7
0.3 1.0
3.5 3.5
2.0 2.0
3.6 3.8
+3.0,-1.2 +3.6,-2.0
+3.0,-1.6
+40,-12 +40,-20
+40,-16
0.6
2.0
3.5
2.0
3.8
+3.6,-2.5
+40,-30
%
M
pF
pF
V
V
V
mA
mA
ILIN
RIN
CIN
CIN
VO
VOL
VOL
IO
IO
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Miscellaneous Ratings
Vcc
Iout output is short circuit protected to
ground, but maximum reliability will be
maintained if Iout does not exceed...
input voltage
maximum junction temperature
operating temperature range
AJ
A8/AM/AL
storage temperature range
lead temperature (soldering 10 sec)
ESD rating
±7.0V Notes:
* AJ : 100% tested at +25°C.
30mA
±Vcc
+150°C
-40°C to +85°C
-55°C to +125°C
-65°C to +150°C
+300°C
1000V
Package Thermal Resistance
Package
Plastic (AJP)
Surface Mount (AJE)
SOT
θJC
70°C/W
65°C/W
130°C/W
θJA
125°C/W
145°C/W
200°C/W
Reliability Information
Transistor count
17
http://www.national.com
2









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CLC109AJP Даташит, Описание, Даташиты
Electrical Characteristics (VCC=+3V or VCC=+5V, -Vee= 0V, TA=+25°C, RL = 100, unless noted)
PARAMETERS
CONDITIONS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
gain flatness
flatness
Vout < 0.5Vpp
Vout < 2.0Vpp
Vout < 0.5Vpp
DC to 30MHz
peaking
DC to 200MHz
rolloff
DC to 60MHz
TIME DOMAIN RESPONSE
rise and fall time
overshoot
slew rate
0.5V step
2.0V step
0.5V step
0.5V step
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
0.5Vpp,20MHz
1.0Vpp,20MHz
3rd harmonic distortion
0.5Vpp,20MHz
1.0Vpp,20MHz
STATIC DC PERFORMANCE
small-signal gain
supply current
AC-coupled
RL=
VCC = 3V VCC = 5V
30 90
35
3 0.3
00
1.5
13.9 4.7
13.5
00
35 200
-32
-37
-29
-43
0.89 0.94
0.75 1.6
UNITS
MHz
MHz
dB
dB
dB
ns
ns
%
V/µs
dBc
dBc
dBc
dBc
V/V
mA
MISCELLANEOUS PERFORMANCE
output voltage range
RL=
RL=100
1.5 2.8 Vpp
1.1 2.6 Vpp
Operation
The CLC109 is a low-power, high-speed unity-gain buffer.
It uses a closed-loop topology which allows for accuracy
not usually found in high-speed buffers. A closed-loop
design provides high accuracy and low output impedance
through a wide bandwidth.
Single Supply Operation
Although the CLC109 is specified to operate from split
±5V power supplies, there is no internal ground reference
that prevents operation from a single voltage power
supply. For single supply operation the input signal should
be biased at a DC value of ½VCC. This can be
accomplished by AC coupling and rebiasing as shown in
the "Typical Application" illustrations on the front page.
The above electrical specifications provide typical
performance specifications for the CLC109 at 25°C while
operating from a single +3V or a single +5V power supply.
Printed Circuit Layout and Supply Bypassing
As with any high-frequency device, a good PCB layout is
required for optimum performance. This is especially
important for a device as fast as the CLC109.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in
Figure 1. Input and output traces should be laid out as
transmission lines with the appropriate termination resistors
very near the CLC109. On a 0.065 inch epoxy PCB
material, a 50transmission line (commonly called stripline)
can be constructed by using a trace width of 0.1" over a
complete ground plane.
Figure 1 shows recommended power supply bypassing.
Parasitic or load capacitance directly on the output of the
CLC109 will introduce additional phase shift in the device.
+5V
C3
6.8µF
+
0.01µF
C1
1
Vin
Rin is chosen
for desired
input impedance.
4
Rin
CLC109 8
2367
5
Rout
Vout
-5V
C4
6.8µF
+
C2
0.01µF
Rout is chosen for
desired output impedance.
(CLC109 Ro= 2.8)
Figure 1: Recommended circuit & evaluation
board schematic
This phase shift can decrease phase margin and increase
frequency response peaking. A small series resistor
inserted between pin 6 and the capacitance effectively
decouples this effect. The graphs on the following page
illustrate the required resistor value and the resulting
performance vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications.
Precision carbon composition resistors or standard spirally-
trimmed RN55D metal film resistors will work, though they
may cause a slight degradation of ac performance due to
their reactive nature at high frequencies.
Evaluation Boards
Evaluation boards are available from National as part
CLC730012 (DIP) and CLC730045 (SOIC). This board
was used in the characterization of the device and provides
optimal performance. Designers are encouraged to copy
these printed circuit board layouts for their applications.
3 http://www.national.com










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