PDF S6E1C31D0A Data sheet ( Hoja de datos )

Número de pieza	S6E1C31D0A
Descripción	Microcontroller
Fabricantes	Cypress Semiconductor
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No Preview Available ! S6E1C3 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller The S6E1C3 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I2C, I2S, Smart Card, and USB). The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral Manual". Features 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40.8 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels 24-bit System timer (Sys Tick): System timer for OS task management Bit Band Operation Compatible with Cortex-M3 bit band operation. On-Chip Memory Flash memory  Up to 128 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM .  Up to 16 Kbytes  4Kbytes: can retain value in Deep standby Mode USB Interface USB interface is composed of Device and Host With Main PLL, USB clock can be generated by multiplication of Main clock. USB Device  USB 2.0 Full-Speed supported  Max 6 EndPoint supported • EndPoint 0 is control transfer • EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer • EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer • EndPoint 1 to 5 comprise Double Buffer • The size of each EndPoint is according to the follows • EndPoint 0, 2 to 5 : 64 bytes • EndPoint 1 : 256 bytes USB host  USB 2.0 Full/Low-Speed supported  Bulk-transfer, Interrupt-transfer and Isochronous-transfer support  USB Device connected/disconnected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported Multi-Function Serial Interface (Max 6channels) 3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels without FIFO (Ch.0, 1 and 3) The operation mode of each channel can be selected from one of the following.  UART  CSIO (CSIO is known to many customers as SPI)  I2C UART  Full duplex double buffer  Parity can be enabled or disabled.  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4) * : S6E1C32B0A/S6E1C31B0A and S6E1C32C0A/S6E1C31C0A do not support Hardware Flow control.  Various error detection functions (parity errors, framing errors, and overrun errors) CSIO (also known as SPI)  Full duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function  Serial chip select function (ch1 and ch6 only)  Data length: 5 to 16 bits I2C  Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400 kbps) supported. I2S (MFS-I2S)  Using CSIO (Max 2 ch: ch.4, ch.6) and I2S clock generator  Supports two transfer protocol • I2S • MSB-justified  Master mode only Cypress Semiconductor Corporation Document Number: 002-00233 Rev.B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 4, 2016 1 page S6E1C3 Series Sales, Solutions, and Legal Information........................................................................................................................... 107 Document Number: 002-00233 Rev.B Page 5 of 107 5 Page WNY048 (TOP VIEW) S6E1C3 Series Note: − The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: 002-00233 Rev.*B Page 11 of 107 11 Page

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