DataSheet26.com

NT5DS128M4CG PDF даташит

Спецификация NT5DS128M4CG изготовлена ​​​​«Nanya Techology» и имеет функцию, называемую «512Mb DDR SDRAM».

Детали детали

Номер произв NT5DS128M4CG
Описание 512Mb DDR SDRAM
Производители Nanya Techology
логотип Nanya Techology логотип 

30 Pages
scroll

No Preview Available !

NT5DS128M4CG Даташит, Описание, Даташиты
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Features
• DDR 512M bit, Die C, based on 90nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.6V ± 0.1V (DDR400)
• VDD = VDDQ = 2.5V ± 0.2V (DDR333)
• RoHS compliance
Description
Die C of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 90 nm design process.
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
REV 1.0
Dec 2007
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS128M4CG Даташит, Описание, Даташиты
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Ordering Information (Lead-Free)
Org.
Part Number
Package
128M x 4
64M x 8
32M x 16
NT5DS128M4CS-5T
NT5DS128M4CS-6K
NT5DS128M4CG-5T
NT5DS128M4CG-6K
NT5DS64M8CS-5T
NT5DS64M8CS-6K
NT5DS64M8CG-5T
NT5DS64M8CG-6K
NT5DS32M16CS-5T
NT5DS32M16CS-6K
NT5DS32M16CG-5T
NT5DS32M16CG-6K
66 pin TSOP-II
60ball BGA
0.8mmx1.0mm
Pitch
66 pin TSOP-II
60ball BGA
0.8mmx1.0mm
Pitch
66 pin TSOP-II
60ball BGA
0.8mmx1.0mm
Pitch
Speed
Clock (MHz)
200
CL-tRCD-tRP
3-3-3
166 2.5-3-3
200 3-3-3
166 2.5-3-3
200 3-3-3
166 2.5-3-3
200 3-3-3
166 2.5-3-3
200 3-3-3
166 2.5-3-3
200 3-3-3
166 2.5-3-3
Comments
DDR400
DDR333
DDR400
DDR333
DDR400
DDR333
DDR400
DDR333
DDR400
DDR333
DDR400
DDR333
REV 1.0
Dec 2007
2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS128M4CG Даташит, Описание, Даташиты
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Pin Configuration - 400mil TSOP II (x4 / x8 / x16)
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NU
LDM*
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
32Mb x 16
64Mb x 8
128Mb x 4
Column Address Table
Organization
128Mb x 4
Column Address
A0-A9, A11, A12
64Mb x 8
A0-A9, A11
32Mb x 16
A0-A9
*DM is internally loaded to match DQ and DQS identically.
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
REV 1.0
Dec 2007
3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










Скачать PDF:

[ NT5DS128M4CG.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
NT5DS128M4CG512Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS128M4CG512Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS128M4CS512Mb DDR SDRAMNanya Techology
Nanya Techology

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск