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PDF CLC426 Data sheet ( Hoja de datos )
| Número de pieza | CLC426 | |
| Descripción | Wideband/ Low-Noise/ Voltage Feedback Op Amp | |
| Fabricantes | National Semiconductor | |
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N
CLC426
Wideband, Low-Noise, Voltage Feedback Op Amp
June 1999
General Description
The CLC426 combines an enhanced voltage-feedback architecture
with an advanced complementary bipolar process to provide a
high-speed op amp with very low noise (1.6nV/√Hz & 2.0pA/√Hz) and
distortion (-62/-68dBc 2nd/3rd harmonics at 1Vpp and 10MHz).
Providing a wide 230MHz gain-bandwidth product, a fast 400V/µs
slew rate and very quick 16ns settling time to 0.05% , the CLC426 is
the ideal choice for high speed applications requiring a very wide-
dynamic range such as an input buffer for high-resolution analog-to-
digital converters.
The CLC426 is internally compensated for gains ≥ 2V/V and can
easily be externally compensated for unity-gain stability in applications
such as wideband low-noise integrators. The CLC426 is also equipped
with external supply current adjustment which allows the user to
optimize power, bandwidth, noise and distortion performance for each
application.
The CLC426's combination of speed, low noise and distortion and low
dc errors will allow high-speed signal conditioning applications to
achieve the highest signal-to-noise performance. To reduce design
times and assist board layout, the CLC426 is supported by an
evaluation board and SPICE simulation model available from National.
For even higher gain-bandwidth voltage-feedback op amps see the
1.9GHz CLC425 (Av ≥ 10V/V) or the 5.0GHz CLC422 (Av ≥ 30V/V).
Features
s Wide gain-bandwidth product: 230MHz
s Ultra-low input voltage noise: 1.6nV/√Hz
s Very low harmonic distortion: -62/-68dBc
s Fast slew rate: 400V/µs
s Adjustable supply current
s Dual ±2.5 to ±5V or single 5 to 12V supplies
s Externally compensatable
Applications
s Active filters & integrators
s Ultrasound
s Low-power portable video
s ADC/DAC buffer
s Wide dynamic range amp
s Differential amps
s Pulse/RF amp
Typical Application
Wide Dynamic Range
Sallen-Key Band Pass Filter
2nd-Order
(20MHz, Q=10, G=2)
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Pinout
DIP & SOIC
NC 1
Vinv 2
Vnon-inv 3
-Vcc 4
-
+
8 Rp (optional)
7 +Vcc
6 Vout
5 Ext. Comp.
(optional)
http://www.national.com
1 page  
Supply Current Adjustment
The CLC426's supply current can be externally adjusted
downward from its nominal value to less than 2mA by
adding an optional resistor (Rp) between pin 8 and the
negative supply as shown in fig 2. The plot labeled "Open-
Loop Gain vs. Supply Current" illustrates the influence
that supply current has over the CLC426's open-loop
tive Load".
Fig. 4
Fig. 2
response. From the plot it is seen that the CLC426 can be
compensated for unity-gain stability by simply lowering
its supply current. Therefore lowering the CLC426's sup-
ply current effectively reduces its open-loop gain to the
point that there is adequate phase margin at unity gain
crossover. The plot labeled "Supply Current vs. Rp"
provides the means for selecting the value of Rp that
produces the desired supply current. The curve in the plot
represents nominal processing but a ±12% deviation over
process can be expected. The two plots labeled "Voltage
Noise vs. Supply Current" and "Current Noise vs. Supply
Current" illustrate the CLC426 supply current's effect over
its input-referred noise characteristics.
Driving Capacitive Loads
The CLC426 is designed to drive capacitive loads with the
addition of a small series resistor placed between the
output and the load as seen in fig. 3. Two plots located in
Faster Settling
The circuit of fig. 5 shows an alternative method for driving
capacitive loads that results in quicker settling times. The
small series-resistor, Rs, is used to decouple the CLC426's
open-loop output resistance, Rout, from the load capaci-
tance. The small feedback-capacitance, Cf, is used to
Fig. 5
provide a high-frequency bypass between the output and
inverting input. The phase lead introduced by Cf compen-
sates for the phase lag due to CL and therefore restores
stability. The following equations provide values of Rs and
Cf for a given load capacitance and closed-loop amplifier
gain.
Fig. 3
the Typical Performance section illustrate this technique
for both frequency domain and time domain applications.
The plot labeled "Frequency Response vs. Capacitive
Load" shows the CLC426's resulting AC response to
various capacitive loads. The values of Rs in this plot
were chosen to maximize the CLC426's AC response
(limited to ≤1dB peaking).
Rs
=
Rout
Rf
Rg
;
where Rout
≈ 6Ω
Eq. 1
C1
=
1+
Rf
Rg
2
CL
Rout
Rg
Eq. 2
The plot in
fig. 6 shows
the result of the two methods of capacitive load driving
mentioned above while driving a 100pF||1kΩ load.
The second plot labeled "Settling Time vs. Capacitive
Load" provides the means for the selection of the value of
Rs which minimizes the CLC426's settling time. As seen
from the plot, for a given capacitive load Rs is chosen from
the curve labeled "Rs". The resulting settling time to
0.05% can then be estimated from the curve labeled "Ts
to 0.05%". The plot of fig. 4 shows the CLC426's pulse
response for various capacitive loads where Rs has been
chosen from the plot labeled "Settling Time vs. Capaci-
5
Fig. 6
http://www.national.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CLC426.PDF ] | |
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