|
|
PDF CLC449 Data sheet ( Hoja de datos )
| Número de pieza | CLC449 | |
| Descripción | 1.1GHz Ultra-Wideband Monolithic Op Amp | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CLC449 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
N
CLC449
1.1GHz Ultra-Wideband Monolithic Op Amp
June 1999
General Description
The CLC449 is an ultra-high-speed monolithic op amp, with a typ-
ical -3dB bandwidth of 1.1GHz at a gain of +2. This wideband op
amp supports rise and fall times less than 1ns, settling time of 6ns
(to 0.2%) and slew rate of 2500V/µs. The CLC449 achieves 2nd
harmonic distortion of -68dBc at 5MHz at a low supply current of
only 12mA. These performance advantages have been achieved
through improvements in National’s proven current feedback
topology combined with a high-speed complementary bipolar
process.
The DC to 1.2GHz bandwidth of the CLC449 is suitable for many IF
and RF applications as a versatile op amp building block for replace-
ment of AC coupled discrete designs. Operational amplifier
functions such as active filters, gain blocks, differentiation, addition,
subtraction and other signal conditioning functions take full
advantage of the CLC449’s unity-gain stable closed-loop
performance.
The CLC449 performance provides greater headroom for lower
frequency applications such as component video, high-resolution
workstation graphics, and LCD displays. The amplifier’s 0.1dB
gain flatness to beyond 200MHz, plus 0.8ns 2V rise and fall times
are ideal for improved time domain performance. In
addition, the 0.03%/0.02° differential gain/phase performance
allows system flexibility for handling standard NTSC and PAL
signals.
In applications using high-speed flash A/D and D/A converters, the
CLC449 provides the necessary wide bandwidth (1.1GHz), settling
(6ns to 0.2%) and low distortion into 50Ω loads to improve SFDR.
Features
s 1.1GHz small-signal bandwidth (Av = +2)
s 2500V/µs slew rate
s 0.03%, 0.02° DG, DΦ
s 6ns settling time to 0.2%
s 3rd order intercept, 30dBm @ 70MHz
s Dual ±5V or single 10V supply
s High output current: 90mA
s 2.5dB noise figure
Applications
s High performance RGB video
s RF/IF amplifier
s Instrumentation
s Medical electronics
s Active filters
s High-speed A/D driver
s High-speed D/A buffer
Frequency Response (Av = +2V/V)
Typical Application
120MSPS High-Speed Flash ADC Driver
Pinout
DIP & SOIC
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
1 page  
Vcc
6.8µF
+
Rt 3 + 7 0.1µF
CLC449 6
Vin Rg
2-
4
Rf
0.1µF
Vo
+
6.8µF
Vee
Figure 2: Inverting Gain
The normalized gain plots in the Typical Performance
Characteristics section show different feedback resistors,
Rf, for different gains. These values of Rf are recommended
for obtaining the highest bandwidth with minimal peaking.
The resistor Rt in Figure 2 provides DC bias for the non-
inverting input.
For |Av| ≤ 4, calculate the recommended Rf as follows:
Rf ≅ 295 - |Av| • Ri, where Ri = 45Ω. For |Av| > 4, the
minimum recommended feedback resistor is Rf = 100 Ω.
Select Rg to set
At large gains,
the
Rg
DC gain:
becomes
Rsgm=a|llARavf n|d
will
load
the
previous stage. This situation is resolved by driving
Rg with a low impedance buffer like the CLC111,
or increasing Rf and Rg (see the Bandwidth (Small
Signal) sub-section for the tradeoffs).
Accurate DC gain is usually limited by the tolerance of
the external resistors Rf and Rg.
Bandwidth (Small Signal)
The CLC449 current-feedback amplifier bandwidth is a
function of the feedback resistor (Rf), not of the DC volt-
age gain (Av). The bandwidth is approximately
proportional to 1/Rf. As a rule, if Rf doubles, the band-
width is cut in half. Other AC specifications will also be
degraded. Decreasing Rf from the recommended
value increases peaking and for very small values of
Rf oscillation will occur.
With an inverting amplifier design, peaking is sometimes
observed. This is often the result of layout parasitics
caused by inadequate ground planes or long traces. If
this is observed, placing a 50 to 200Ω resistor between
the non-inverting pin and ground will usually reduce the
peaking.
Bandwidth (Minimum Slew Rate)
Slew rate influences the bandwidth for large signal
sinusoids. To determine an approximate value of slew
rate, necessary to support large sinusoids use the
following equation:
SR ≅ 5 • f • Vpeak
Vpeak is the peak output sinusoidal voltage, f is the
frequency of the sinusoid.
The slew rate of the CLC449 in inverting gains is always
higher than in non-inverting gains.
DC Design (Level Shifting)
Figure 3 shows a DC level shifting circuit for inverting
gain configurations. Vref produces a DC output level shift
of
which-iVsreinf ⋅dReRprefef ndent of the DC output produced by Vin.
Figure 3: Level Shifting Circuit
Req1
Vin Req2
Vref Rref
+
CLC449
-
Rf
Vo
DC Design (Single Supply)
Figure 4 is a typical single-supply circuit. Resistors R1
and R2 form a voltage divider that sets the non-inverting
input DC voltage. This circuit has a DC gain of 1. The
coupling capacitor C1 isolates the DC bias point from the
previous stage. Both capacitors make a high pass
response; the high frequency gain is determined by Rf
and Rg.
Vcc
R1
Vin
C1
R2
Vcc
+
CLC449
-
Rf
Vo
Rg
C2
Figure 4: Single Supply Circuit
The complete gain equation for the circuit in Figure 4 is:
Vo =
sτ1
⋅
1+
sτ2
⋅
1+
Rf
Rg
Vin 1+ sτ1
1+ sτ2
where s = jω, τ1 = (R1|| R2) • C1, and τ2 = RgC2.
DC Design (DC Offsets)
The DC offset model shown in Figure 5 is used to
calculate the output offset voltage. The equation for out-
put offset voltage is:
( ) ( )Vo = −
Vos
+ IBN ⋅Req1
⋅
1+
Rf
Req2
+
IBI ⋅Rf
The current offset terms, IBN and IBI, do not track each
other. The specifications are stated in terms of
magnitude only. Therefore, the terms Vos, IBN, and IBI
may have either positive or negative polarity. Matching
the equivalent resistance seen at both input pins does
not reduce the output offset voltage.
5 http://www.national.com
5 Page 
This page intentionally left blank.
11 http://www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CLC449.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CLC440 | High-Speed/ Low-Power/ Voltage Feedback Op Amp | National Semiconductor |
| CLC440 | CLC440 High Speed Low Power Voltage Feedback Op Amp (Rev. B) |  Texas Instruments |
| CLC446 | 400MHz/ 50mW Current-Feedback Op Amp | National Semiconductor |
| CLC446 | CLC446 400MHz 50mW Current-Feedback Op Amp (Rev. B) | Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |