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PDF HD6432653 Data sheet ( Hoja de datos )
| Número de pieza | HD6432653 | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas | |
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REJ09B0331-0500
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2655 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
H8S/2655
H8S/2653
HD6432655
HD6472655
HD6432653
Rev. 5.00
Revision Date: Sep 14, 2006
1 page  
Preface
The H8S/2655 Group is a series of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT*) and mask ROM
versions are available, providing a quick and flexible response to conditions from ramp-up
through full-scale volume production, even for applications with frequently changing
specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2655 Group enables compact, high-performance systems to be implemented
easily.
This manual describes the hardware of the H8S/2655 Group. Refer to the H8S/2600 Series,
H8S/2000 Series Software Manual for a detailed description of the instruction set.
Note: * ZTAT is a registered trademark of Renesas Technology Corp.
Rev. 5.00 Sep 14, 2006 page v of xxviii
5 Page 
Item
B.2 Functions
Page
998
1004
1010
Appendix G Package
Dimensions
Figure G.1 TFP-120
Package Dimensions
Figure G.2 FP-128
Package Dimensions
1058
1059
Revision (See Manual for Details)
TSR0 H'FFD5 TPU0
Figure amended
TGR Input Capture/Output Compare Flag A
TGR Input Capture/Output Compare Flag B
TGR Input Capture/Output Compare Flag C
TGR Input Capture/Output Compare Flag D
TSR1 H'FFE5 TPU1
Figure amended
TGR Input Capture/Output Compare Flag A
TGR Input Capture/Output Compare Flag B
TSR2 H'FFF5 TPU2
Figure amended
TGR Input Capture/Output Compare Flag A
TGR Input Capture/Output Compare Flag B
Figure G.1 replaced
Figure G.2 replaced
Rev. 5.00 Sep 14, 2006 page xi of xxviii
11 Page | ||
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| PDF Descargar | [ Datasheet HD6432653.PDF ] | |
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