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CLC5902VLA PDF даташит

Спецификация CLC5902VLA изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Dual Digital Tuner/AGC».

Детали детали

Номер произв CLC5902VLA
Описание Dual Digital Tuner/AGC
Производители National Semiconductor
логотип National Semiconductor логотип 

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CLC5902VLA Даташит, Описание, Даташиты
N
May 1999
CLC5902
Dual Digital Tuner/AGC
0
0
General Overview
The CLC5902 Dual Digital Tuner/AGC IC is a two channel digital
downconverter (DDC) with integrated automatic gain control
(AGC). The CLC5902 is a key component in the Diversity
Receiver Chipset (DRCS) which includes one CLC5902 Dual
Digital Tuner/AGC, two CLC5956 12-bit analog-to-digital
converters (ADCs), and two CLC5526 digitally controlled variable
gain amplifiers (DVGAs). A block diagram for a Diversity
Receiver Chipset based narrowband communications system is
shown in Figure 1. This system allows direct IF sampling of signals
up to 300MHz for enhanced receiver performance and reduced
system costs.
The CLC5902 offers high dynamic range digital tuning and
filtering based on hard-wired digital signal processing (DSP)
technology. Each channel has independent tuning, phase offset, and
gain settings. Channel filtering is performed by a series of three
filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter
with a programmable decimation ratio from 8 to 2048. Next there
are two symmetric FIR filters, a 21-tap and a 63-tap, both with
programmable coefficients. The first FIR filter decimates the data
by 2, the second FIR decimates by either 2 or 4. Channel filter
bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz.
The CLC5902’s AGC controller monitors the ADC output and
controls the ADC input signal level by adjusting the DVGA setting.
AGC threshold, deadband+hysteresis, and the loop time constant
are user defined. Total dynamic range of greater than 120dB full-
scale signal to noise can be achieved with the Diversity Receiver
Chipset.
Features
n 52MSPS Operation
n Two Independent Channels with
14-bit inputs
n Greater than 100 dB image rejec-
tion
n Greater than 100 dB spurious free
dynamic range
n 0.02 Hz tuning resolution
n User Programmable AGC
n Channel Filters include a Fourth
Order CIC followed by 21-tap and
63-tap Symmetric FIRs
n FIR filters process 21-bit Data
with 16-bit Programmable Coeffi-
cients
n Flexible output formats include
12-bit Floating Point or 8, 16, 24,
and 32 bit Fixed Point
n Serial and Parallel output ports
n JTAG Boundary Scan
n 8-bit Microprocessor Interface
n 380mW/channel, 52 MHz, 3.3V
n 128 pin PQFP package
Applications
n Cellular Basestations
n Satellite Receivers
n Wireless Local Loop Receivers
n Digital Communications
CLC5526
LC
IF A DVGA
IF B
CLK
DVGA
LC
CLC5956
ADC
12
ADC
4
12
CLC5902
Dual Digital
Tuner/AGC
Figure 1
Diversity Receiver Chipset Block Diagram
©1999 National Semiconductor Corporation
SerialOutA/B
SerialOutB
SCK
SFS
RDY
ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
Rev. 3.05 May 27, 1999









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CLC5902VLA Даташит, Описание, Даташиты
RD
WR
CE
A[7:0]
D[7:0]
AIN
BIN
Microprocessor
Interface
MUX 14
A
MUX 14
B
TEST_REG
Input Source
A_SOURCE
B_SOURCE
CK
SI
MR
AGC_EN
CLK
GEN
Sync
Logic
Channel A Controls
GAIN_A AGC_IC_A
FREQ_A AGC_RB_A
PHASE_A DITH_A
AGAIN[2..0]
ASTROBE
Channel A
Tuning,
Channel Filters, and
AGC (see Figure 14)
Channel B
Tuning,
Channel Filters, and
AGC (see Figure 14)
Output Formatter
Floating Point:
4-bit Exponent and
8-bit Mantissa
or
Two’s Complement:
32-bit Truncated or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated
(see Figure 26)
AOUT/BOUT
BOUT
SCK
SFS
RDY
POUT[15..0]
PSEL[2..0]
POUT_EN
Channel B Controls
GAIN_B AGC_IC_B
FREQ_B AGC_RB_B
PHASE_B DITH_B
Common Channel Controls
DEC
DEC_BY_4
SCALE
EXP_INH
F1_COEFF
F2_COEFF
AGC_FORCE
AGC_RESET_EN
AGC_HOLD_IC
AGC_LOOP_GAIN
AGC_COUNT
AGC_TABLE
Output Controls
RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP
BSTROBE
BGAIN[2..0]
Figure 2
CLC5902 Dual Digital Tuner/AGC Block Diagram with Control Register Associations
Functional Description.
The CLC5902 block diagram is shown in Figure 2. The
CLC5902 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts a 14-bit sample at up
to 52MSPS, down converts from a selected carrier fre-
quency to baseband, decimates the signal rate by a pro-
grammable factor ranging from 32 to 16384, provides
channel filtering, and outputs quadrature symbols.
A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC channel. Flexible chan-
nel filtering is provided by the two programmable deci-
mating FIR filters. The final filter outputs can be
converted to a 12-bit floating point format or standard
two’s complement format. The output data is available at
both serial and parallel ports.
The CLC5902 maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection.
This allows considerable latitude in channel filter parti-
tioning between the analog and digital domains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can
be independently specified. Both channels share the same
decimation ratio, bandwidth, filter coefficients, and input/
output formats.
Each channel has its own AGC circuit for use with nar-
rowband radio channels where most of the channel filter-
ing precedes the ADC. The AGC closes the loop around
the CLC5526 DVGA, compressing the dynamic range of
the signal into the ADC. The AGC can be configured to
operate continuously or in a gated mode. The two AGC
circuits operate independently but share the same pro-
grammed parameters and control signals.
The chip receives configuration and control information
over a microprocessor-compatible bus consisting of an 8-
bit data I/O port, an 8-bit address port, a chip enable
strobe, a read strobe, and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 8-bit
address space of the control port.
JTAG boundary scan and on-chip diagnostic circuits are
provided to simplify system debug and test.
The CLC5902 supports 3.3V I/O. The CLC5956 ADC
outputs are compatible with the CLC5902 inputs. The
CLC5902 outputs swing to the 3.3V rail so they can be
directly connected to 5V TTL inputs if desired.
Rev. 3.05 May 27, 1999
2 ©1999 National Semiconductor Corporation









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CLC5902VLA Даташит, Описание, Даташиты
CLC5902 Electrical Characteristics
(VCC=+3.3V, 52MHz, CIC Decimation=48, F2 Decimation=2, Tmin=-40°C, Tmax=+85°C; unless specified)
DC Characteristics
PARAMETER
Voltage input low
Voltage input high
Input current
Voltage output low (IOL = 4mA/12mA, see pin description)
Voltage output high (IOH = -4mA/-12mA, see pin description)
Input capacitance
AC Characteristics
SYMBOL
VIL
VIH
IIN
VOL
VOH
CIN
MIN
-0.5
2.0
2.4
TYP
MAX
UNITS
0.8
VCC+0.5
10
0.4
4.0
V
V
uA
V
V
pF
Notes
1
1
1
1
1
3
PARAMETER (CL=50pF)
Clock (CK) Frequency (Figure 7)
Spurious Free Dynamic Range
Signal to Noise Ratio
Tuning Resolution
Phase Resolution
MR Active Time (Figure 5)
MR Inactive to first Control Port Access (Figure 5)
MR Setup Time to CK (Figure 5)
MR Hold Time to CK (Figure 5)
MR Inactive to A|BSTROBE Release (Figure 5)
SI Setup Time to CK (Figure 6)
SI Hold Time from CK (Figure 6)
SI Pulse Width (Figure 6)
SI Inactive to A|BSTROBE Release (Figure 6)
CK duty cycle (Figure 7)
CK rise and fall times (VIL to VIH) (Figure 7)
Input setup before CK goes high (A|BIN) (Figure 7)
Input hold time after CK goes high (Figure 7)
A|BSTROBE Pulse Width (Figure 8)
A|BGAIN Valid Setup before A|BSTROBE (Figure 8)
AGC_EN Active Width (Figure 8)
SCK to SFS Valid (Table Note A) (Figure 9)
SCK to A|BOUT Valid (Table Note B) (Figure 9)
RDY Pulse Width (Figure 9)
POUT_EN Active to POUT[15..0] Valid (Figure 10)
POUT_EN Inactive to POUT[15..0] Tri-State (Figure 10)
PSEL[2..0] to POUT[15..0] Valid (Figure 11)
RDY to POUT[15..0] New Value Valid (Table Note C) (Figure 12)
Propagation Delay TCK to TDO (Figure 13)
Propagation Delay TCK to Data Out (Figure 13)
Disable Time TCK to TDO (Figure 13)
Disable Time TCK to Data Out (Figure 13)
Enable Time TCK to TDO (Figure 13)
SYMBOL
FCK
SFDR
SNR
MIN
tMRA
tMRIC
tMRSU
tMRH
tMRSR
tSISU
tSIH
tSIW
tSISR
tCKDC
tRF
tSU
tHD
tSTBPW
tGSU
tENW
tSFSV
tOV
tRDYW
tOENV
tOENT
tSELV
tRDYV
tPLH
tPHL
tPLZ
tPHZ
tPZL
4
10
9
2
9
2
4
40
7
3
2
0
0
0
TYP
-100
-127
0.02
0.005
17
17
1
1
4
MAX
52
60
3
7
7
15
15
20
10
30
35
35
35
35
UNITS
Notes
MHz
dBFS
dBFS
Hz
°
CK periods
CK periods
ns
ns
ns
ns
ns
CK periods
ns
%
ns
ns
ns
CK period
CK period
CK periods
ns
ns
CK periods
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
©1999 National Semiconductor Corporation
3
Rev. 3.05 May 27, 1999










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Номер в каталогеОписаниеПроизводители
CLC5902VLADual Digital Tuner/AGCNational Semiconductor
National Semiconductor

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