DataSheet26.com

CLC5903VLA PDF даташит

Спецификация CLC5903VLA изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Dual Digital Tuner / AGC».

Детали детали

Номер произв CLC5903VLA
Описание Dual Digital Tuner / AGC
Производители National Semiconductor
логотип National Semiconductor логотип 

29 Pages
scroll

No Preview Available !

CLC5903VLA Даташит, Описание, Даташиты
June 2004
N National Semiconductor
CLC5903
Dual Digital Tuner / AGC
0
0
General Overview
The CLC5903 Dual Digital Tuner / AGC IC is a two channel
digital downconverter (DDC) with integrated automatic gain
control (AGC). The CLC5903 is a key component in the
Enhanced Diversity Receiver Chipset (EDRCS) which
includes one CLC5903 Dual Digital Tuner / AGC, two
CLC5957 12-bit analog-to-digital converters (ADCs), and two
CLC5526 digitally controlled variable gain amplifiers
(DVGAs). This system allows direct IF sampling of signals up
to 300MHz for enhanced receiver performance and reduced
system costs.
The CLC5903 is an enhanced replacement for the CLC5902
in the Diversity Receiver Chipset (DRCS). The main
improvements relative to the CLC5902 are a 50% increase in
maximum sample rate from 52MHz to 78MHz, a 62%
reduction in power consumption from 760mW to 290mW,
and the added flexibility to independently program filter
coefficients in the two channels. A block diagram for a
DRCS-based narrowband communications system is shown
in Figure 1.
The CLC5903 offers high dynamic range digital tuning and
filtering based on hard-wired digital signal processing (DSP)
technology. Each channel has independent tuning, phase
offset, filter coefficients, and gain settings. Channel filtering
is performed by a series of three filters. The first is a 4-stage
Cascaded Integrator Comb (CIC) filter with a programmable
decimation ratio from 8 to 2048. Next there are two
symmetric FIR filters, a 21-tap and a 63-tap, both with
independent programmable coefficients. The first FIR filter
decimates the data by 2, the second FIR decimates by either
2 or 4. Channel filter bandwidth at 52MSPS ranges from
±650kHz down to ±1.3kHz. At 78MSPS, the maximum
bandwidth increases to ±975kHz.
The CLC5903’s AGC controller monitors the ADC output and
controls the ADC input signal level by adjusting the DVGA
setting. AGC threshold, deadband+hysteresis, and the loop
time constant are user defined. Total dynamic range of
greater than 120dB full-scale signal to noise in a 200kHz
bandwidth can be achieved with the Diversity Receiver
Chipset.
Features
„ 78MSPS Operation
„ Low Power, 145mW/channel, 52 MHz, Dec=192
„ Two Independent Channels with 14-bit inputs
„ Serial Daisy-chain Mode for quad receivers
„ Greater than 100 dB image rejection
„ Greater than 100 dB spurious free dynamic range
„ 0.02 Hz tuning resolution
„ User Programmable AGC with enhanced Power Detector
„ Channel Filters include a Fourth Order CIC followed by
21-tap and 63-tap Symmetric FIRs
„ FIR filters process 21-bit Data with 16-bit Programmable
Coefficients
„ Two independent FIR coefficient memories which can be
routed to either or both channels.
„ Flexible output formats include 12-bit Floating Point or 8,
16, 24, and 32 bit Fixed Point
„ Serial and Parallel output ports
„ JTAG Boundary Scan
„ 8-bit Microprocessor Interface
„ 128 pin PQFP and 128 pin FBGA packages
„ 100% Software compatible with the CLC5902
„ Pin compatible with the CLC5902 except for VDD voltage
Applications
„ Cellular Basestations
„ Satellite Receivers
„ Wireless Local Loop Receivers
„ Digital Communications
IF A
IF B
CLK
CLC5526
DVGA
LC
DVGA
LC
CLC5957
ADC
DAV
12
8
ADC
12
DAV
CLC5903
Dual Digital
Tuner/AGC
Figure 1. Diversity Receiver Chipset Block Diagram
SCK_IN
SerialOutA/B
SerialOutB
SCK
SFS
RDY
ParallelOutput[15..0]
ParallelOutputEnable
ParallelSelect[2..0]
©2004 National Semiconductor Corporation DS200286
www.national.com
Revision 1.6









No Preview Available !

CLC5903VLA Даташит, Описание, Даташиты
RD
WR
CE
A[7:0]
D[7:0]
Microprocessor
Interface
Channel A Controls
GAIN_A FREQ_A COEF_SEL_F1A
PHASE_A DITH_A COEF_SEL_F2A
AGC_IC_A AGC_RB_A
AGAIN[2..0]
ASTROBE
AIN
BIN
MUX 14
A
Channel A
Tuning,
Channel Filters, and
Output Formatter
Floating Point:
4-bit Exponent and
SCK_IN
AOUT/BOUT
BOUT
AGC (see Figure 16)
8-bit Mantissa
SCK
or SFS
MUX 14
B
Channel B
Tuning,
Channel Filters, and
AGC (see Figure 16)
Two’s Complement:
32-bit Truncated or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated
(see Figure 29)
RDY
POUT[15..0]
PSEL[2..0]
POUT_EN
TEST_REG
Input Source
A_SOURCE
B_SOURCE
CKA
CKB
SI
MR
CLK
GEN
Sync
Logic
Channel B Controls
GAIN_B FREQ_B COEF_SEL_F1B
PHASE_B DITH_B COEF_SEL_F2B
AGC_IC_B AGC_RB_B
Common Channel Controls
DEC
DEC_BY_4
SCALE
EXP_INH
EXT_DELAY
AGC_HOLD_IC
AGC_LOOP_GAIN
AGC_TABLE
AGC_COMB_ORD
PAGE_SEL_F1
F1A_COEFF
F1B_COEFF
PAGE_SEL_F2
F2A_COEFF
F2B_COEFF
BSTROBE
BGAIN[2..0]
Output Controls
RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP
SFS_MODE
SDC_EN
Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations
Functional Description
The CLC5903 block diagram is shown in Figure 2. The
CLC5903 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts an independently clocked
14-bit sample at up to 78MSPS, down converts from a
selected carrier frequency to baseband, decimates the signal
rate by a programmable factor ranging from 32 to 16384, pro-
vides channel filtering, and outputs quadrature symbols.
A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC channel. Flexible channel
filtering is provided by the two programmable decimating FIR
filters. The final filter outputs can be converted to a 12-bit
floating point format or standard two’s complement format.
The output data is available at both serial and parallel ports.
The CLC5903 maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection.
This allows considerable latitude in channel filter partitioning
between the analog and digital domains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can be
independently specified. Two sets of coefficient memories
and a crossbar switch allow shared or independent filter
coefficients and bandwidth for each channel. Both channels
share the same decimation ratio and input/output formats.
Each channel has its own AGC circuit for use with narrow-
band radio channels where most of the channel filtering pre-
cedes the ADC. The AGC closes the loop around the
CLC5526 DVGA, compressing the dynamic range of the sig-
nal into the ADC. AGC gain compensation in the CLC5903
removes the DVGA gain steps at the output. The time align-
ment of this gain compensation circuit can be adjusted to
support ADCs with different latencies. The AGC can be con-
figured to operate continuously or set to a fixed gain step.
The two AGC circuits operate independently but share the
same programmed parameters and control signals.
The chip receives configuration and control information over
a microprocessor-compatible bus consisting of an 8-bit data
I/O port, an 8-bit address port, a chip enable strobe, a read
strobe, and a write strobe. The chip’s control registers (8 bits
each) are memory mapped into the 8-bit address space of
the control port. Page select bits allow access to the overlaid
A and B set of FIR coefficients.
JTAG boundary scan and on-chip diagnostic circuits are pro-
vided to simplify system debug and test.
The CLC5903 supports 3.3V I/O even though the core logic
voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail
so they can be directly connected to 5V TTL inputs if desired.
www.national.com
2









No Preview Available !

CLC5903VLA Даташит, Описание, Даташиты
Absolute Maximum Ratings
Positive IO Supply Voltage (VDDIO)
Positive CoreSupply Voltage (VDD)
Voltage on Any Input or Output Pin
Input Current at Any Pin
-0.3V to 4.2V
-0.3V to 2.4V
-0.3V to VDDIO+0.5V
±25mA
Package Input Current
±50mA
Package Dissipation at TA=25°C
ESD Susceptibility
Human Body Model
Machine Model
1W
2000V
200V
Soldering Temperature, Infrared, 10
seconds
300°C
Storage Temperature
-65°C to 150°C
NOTE: Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability of the
circuit may be impaired. Functional operability under any of
these conditions is not necessarily implied. Exposure to maxi-
mum ratings for extended periods may affect device reliability.
Operating Ratings
Positive IO Supply Voltage (VDDIO)
3.3V ±10%
Positive Core Supply Voltage (VDD)
1.8V ±10%
Operating Temperature Range
-40°C to +85°C
Package Thermal Resistance
Package
θja
128 pin PQFP
128 pin FBGA
39°C/W
30°C/W
Reliability Information
θjc
20°C/W
N/A
Transistor Count
Ordering Information
1.4 million
Order Code
CLC5903VLA
CLC5903SM
Temperature
Range
Description
-40°C to
+85°C
-40°C to
+85°C
128-pin PQFP (indus-
trial temperature range)
128-pin FBGA (indus-
trial temperature range)
CLC5903 Electrical Characteristics (Note 1)
DC Characteristics
(FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified)
Symbol
Parameter
VIL Voltage input low
VIH Voltage input high
IOZ Input current
VOL Voltage output low (IOL = 4mA/16mA, see Note 2)
VOH Voltage output high (IOH = -4mA/-16mA, see Note 2)
CIN Input capacitance
Min Typ Max Units
-0.5 0.7 V
2.3
VDDIO+0.5
V
20 uA
0.4 V
2.4 V
5.0 pF
AC Characteristics
(FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified)
Symbol
FCK
SFDR
SNR
tMRA
tMRIC
Parameter (CL=50pF)
Clock (CKA|B) Frequency (Figure 7)
Spurious Free Dynamic Range
Signal to Noise Ratio
Tuning Resolution
Phase Resolution
MR Active Time (Figure 5)
MR Inactive to first Control Port Access (Figure 5)
Min Typ Max Units
78 MHz
-100
-127
0.02
0.005
dBFS
dBFS
Hz
°
4 CK periods
10 CK periods
3 www.national.com










Скачать PDF:

[ CLC5903VLA.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
CLC5903VLADual Digital Tuner / AGCNational Semiconductor
National Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск