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S25FL128S PDF даташит

Спецификация S25FL128S изготовлена ​​​​«Cypress» и имеет функцию, называемую «3.0V SPI Flash Memory».

Детали детали

Номер произв S25FL128S
Описание 3.0V SPI Flash Memory
Производители Cypress
логотип Cypress логотип 

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S25FL128S Даташит, Описание, Даташиты
S25FL128S/S25FL256S
128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (1.5 Mbytes/s)
– 256 or 512 Byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 Mbytes/s)
– Hybrid sector size option - physical set of thirty two 4-kbyte sectors
at top or bottom of address space with all remaining sectors of
64 kbytes, for compatibility with prior generation S25FL devices
– Uniform sector option - always erase 256-kbyte blocks for software
compatibility with higher density and future devices.
Cycling Endurance
– 100,000 Program-Erase Cycles
Data Retention
– 20 Year Data Retention
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress® 65 nm MirrorBit® Technology with EclipseArchitecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
Temperature Range / Grade:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Extended (-40°C to +125°C)
– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
– Automotive AEC-Q100 Grade 1 (-40°C to +125°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– WSON 6 x 8 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
WP#/IO2
HOLD#/IO3
RESET#
I/O
SRAM
Control
Logic
MirrorBit Array
Y Decoders
Data Latch
Data Path
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98283 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 22, 2016









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S25FL128S Даташит, Описание, Даташиты
S25FL128S/S25FL256S
Performance Summary
Maximum Read Rates with the Same Core and I/O Voltage (VIO = VCC = 2.7V to 3.6V)
Read
Fast Read
Dual Read
Quad Read
Command
Clock Rate (MHz)
50
133
104
104
Maximum Read Rates with Lower I/O Voltage (VIO = 1.65V to 2.7V, VCC = 2.7V to 3.6V)
Read
Fast Read
Dual Read
Quad Read
Command
Clock Rate (MHz)
50
66
66
66
Maximum Read Rates DDR (VIO = VCC = 3V to 3.6V)
Fast Read DDR
Dual Read DDR
Quad Read DDR
Command
Clock Rate (MHz)
80
80
80
Typical Program and Erase Rates
Page Programming (256-byte page buffer - Hybrid Sector Option)
Page Programming (512-byte page buffer - Uniform Sector Option)
4-kbyte Physical Sector Erase (Hybrid Sector Option)
64-kbyte Physical Sector Erase (Hybrid Sector Option)
256-kbyte Logical Sector Erase (Uniform Sector Option)
Operation
Current Consumption
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 104 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Operation
Mbytes/s
6.25
16.6
26
52
Mbytes/s
6.25
8.25
16.5
33
Mbytes/s
20
40
80
kbytes/s
1000
1500
30
500
500
Current (mA)
16 (max)
33 (max)
61 (max)
90 (max)
100 (max)
100 (max)
0.07 (typ)
Document Number: 001-98283 Rev. *J
Page 2 of 149









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S25FL128S Даташит, Описание, Даташиты
S25FL128S/S25FL256S
Contents
Features................................................................................. 1
Logic Block Diagram............................................................ 1
Performance Summary ........................................................ 2
1. Overview ....................................................................... 4
1.1 General Description ....................................................... 4
1.2 Migration Notes.............................................................. 5
1.3 Glossary......................................................................... 7
1.4 Other Resources............................................................ 7
Hardware Interface
2. Signal Descriptions ..................................................... 8
2.1 Input/Output Summary................................................... 8
2.2 Address and Data Configuration.................................... 9
2.3 RESET# ......................................................................... 9
2.4 Serial Clock (SCK) ......................................................... 9
2.5 Chip Select (CS#) .......................................................... 9
2.6 Serial Input (SI) / IO0 ................................................... 10
2.7 Serial Output (SO) / IO1............................................... 10
2.8 Write Protect (WP#) / IO2 ............................................ 10
2.9 Hold (HOLD#) / IO3 ..................................................... 10
2.10 Core Voltage Supply (VCC) .......................................... 11
2.11 Versatile I/O Power Supply (VIO) ................................. 11
2.12 Supply and Signal Ground (VSS) ................................. 11
2.13 Not Connected (NC) .................................................... 11
2.14 Reserved for Future Use (RFU)................................... 11
2.15 Do Not Use (DNU) ....................................................... 11
2.16 Block Diagrams............................................................ 12
3. Signal Protocols......................................................... 13
3.1 SPI Clock Modes ......................................................... 13
3.2 Command Protocol ...................................................... 14
3.3 Interface States............................................................ 18
3.4 Configuration Register Effects on the Interface ........... 22
3.5 Data Protection ............................................................ 22
4. Electrical Specifications............................................ 24
4.1 Absolute Maximum Ratings ......................................... 24
4.2 Thermal Resistance ..................................................... 24
4.3 Operating Ranges........................................................ 24
4.4 Power-Up and Power-Down ........................................ 25
4.5 DC Characteristics ....................................................... 28
5. Timing Specifications................................................ 29
5.1 Key to Switching Waveforms ....................................... 29
5.2 AC Test Conditions ...................................................... 29
5.3 Reset............................................................................ 30
5.4 SDR AC Characteristics............................................... 32
5.5 DDR AC Characteristics .............................................. 36
6. Physical Interface ...................................................... 38
6.1 SOIC 16-Lead Package ............................................... 38
6.2 WSON Package........................................................... 40
6.3 FAB024 24-Ball BGA Package .................................... 41
6.4 FAC024 24-Ball BGA Package .................................... 43
Software Interface
7. Address Space Maps.................................................. 45
7.1 Overview....................................................................... 45
7.2 Flash Memory Array...................................................... 45
7.3 ID-CFI Address Space .................................................. 47
7.4 OTP Address Space ..................................................... 47
7.5 Registers....................................................................... 48
8. Data Protection ........................................................... 57
8.1 Secure Silicon Region (OTP)........................................ 57
8.2 Write Enable Command................................................ 57
8.3 Block Protection ............................................................ 58
8.4 Advanced Sector Protection ......................................... 59
9. Commands .................................................................. 63
9.1 Command Set Summary............................................... 64
9.2 Identification Commands .............................................. 70
9.3 Register Access Commands......................................... 72
9.4 Read Memory Array Commands .................................. 83
9.5 Program Flash Array Commands ................................. 99
9.6 Erase Flash Array Commands.................................... 105
9.7 One Time Program Array Commands ........................ 111
9.8 Advanced Sector Protection Commands .................... 112
9.9 Reset Commands ....................................................... 118
9.10 Embedded Algorithm Performance Tables ................. 119
10. Data Integrity ............................................................. 120
10.1 Erase Endurance ........................................................ 120
10.2 Data Retention ............................................................ 120
11. Software Interface Reference .................................. 121
11.1 Command Summary ................................................... 121
11.2 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 123
11.3 Device ID and Common Flash Interface (ID-CFI) ASO Map
— Automotive Only ..................................................... 135
11.4 Registers..................................................................... 135
11.5 Initial Delivery State .................................................... 139
12. Ordering Information ................................................ 140
13. Contacting Cypress .................................................. 142
14. Revision History........................................................ 143
Document Number: 001-98283 Rev. *J
Page 3 of 149










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