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PDF S25FL256S Data sheet ( Hoja de datos )
| Número de pieza | S25FL256S | |
| Descripción | 3.0V SPI Flash Memory | |
| Fabricantes | Cypress | |
| Logotipo |  |
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S25FL128S/S25FL256S
128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (1.5 Mbytes/s)
– 256 or 512 Byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 Mbytes/s)
– Hybrid sector size option - physical set of thirty two 4-kbyte sectors
at top or bottom of address space with all remaining sectors of
64 kbytes, for compatibility with prior generation S25FL devices
– Uniform sector option - always erase 256-kbyte blocks for software
compatibility with higher density and future devices.
Cycling Endurance
– 100,000 Program-Erase Cycles
Data Retention
– 20 Year Data Retention
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress® 65 nm MirrorBit® Technology with Eclipse™ Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
Temperature Range / Grade:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Extended (-40°C to +125°C)
– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
– Automotive AEC-Q100 Grade 1 (-40°C to +125°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– WSON 6 x 8 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
WP#/IO2
HOLD#/IO3
RESET#
I/O
SRAM
Control
Logic
MirrorBit Array
Y Decoders
Data Latch
Data Path
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98283 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 22, 2016
1 page  
S25FL128S/S25FL256S
1.2 Migration Notes
1.2.1
Features Comparison
The S25FL128S and S25FL256S devices are command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1.1 FL Generations Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Fast Read Speed (DDR)
Dual Read Speed (DDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Time (typ.)
Page Programming Time (typ.)
OTP
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FL-K
90 nm
Floating Gate
In Production
4 Mb - 128 Mb
x1, x2, x4
2.7V - 3.6V
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
-
-
-
256B
4 kB / 32 kB / 64 kB
4 kB
30 ms (4 kB), 150 ms (64 kB)
700 µs (256B)
768B (3 x 256B)
No
No
Yes
Yes
-40°C to +85°C
FL-P
90 nm
MirrorBit
In Production
32 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
-
-
-
256B
64 kB / 256 kB
4 kB
500 ms (64 kB)
1500 µs (256B)
506B
No
No
No
No
-40°C to +85°C / +105°C
Notes:
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64-kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Refer to individual data sheets for further details.
FL-S
65 nm
MirrorBit Eclipse
2H2011
128 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V VIO
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
80 MB/s (80 MHz)
256B / 512B
64 kB / 256 kB
4 kB (option)
130 ms (64 kB), 520 ms (256 kB)
250 µs (256B), 340 µs (512B)
1024B
Yes
Yes
Yes
Yes
-40°C to +85°C /
+105°C / +125°C
1.2.2
Known Differences from Prior Generations
1.2.2.1
Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case the program or
erase operation did not complete as requested by the command.
Document Number: 001-98283 Rev. *J
Page 5 of 149
5 Page 
S25FL128S/S25FL256S
Figure 2.1 HOLD Mode Operation
CS#
SCK
HOLD#
SI_or_IO_(during_input)
SO_or_IO_(internal)
SO_or_IO_(external)
Valid Input
A
A
Hold Condition
Standard Use
Don't Care
B
B
Valid Input
C
BC
Hold Condition
Non-standard Use
Don't Care
D
Valid Input
D
E
E
2.10 Core Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase. The voltage may vary from 2.7V to 3.6V.
2.11 Versatile I/O Power Supply (VIO)
The Versatile I/O (VIO) supply is the voltage source for all device input receivers and output drivers and allows the host system to set
the voltage levels that the device tolerates on all inputs and drives on outputs (address, control, and IO signals). The VIO range is
1.65V to VCC. VIO cannot be greater than VCC.
For example, a VIO of 1.65V - 3.6V allows for I/O at the 1.8V, 2.5V or 3V levels, driving and receiving signals to and from other 1.8V,
2.5V or 3V devices on the same data bus. VIO may be tied to VCC so that interface signals operate at the same voltage as the core
of the device. VIO is not available in all package options, when not available the VIO supply is tied to VCC internal to the package.
During the rise of power supplies the VIO supply voltage must remain less than or equal to the VCC supply voltage. This supply is not
available in all package options. For a backward compatible SO16 footprint, the VIO supply is tied to VCC inside the package; thus,
the IO will function at VCC level.
2.12 Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
2.13 Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an
NC must not have voltage levels higher than VIO.
2.14 Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but is there potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
2.15 Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
Document Number: 001-98283 Rev. *J
Page 11 of 149
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S25FL256S.PDF ] | |
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