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PDF CDP1802BC Data sheet ( Hoja de datos )
| Número de pieza | CDP1802BC | |
| Descripción | CMOS 8-Bit Microprocessors | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CDP1802A, CDP1802AC,
CDP1802BC
March 1997
CMOS 8-Bit Microprocessors
[ /Title
(CDP1
802A,
CDP18
02AC,
CDP18
02BC)
/Sub-
ject
(CMO
S 8-
Bit
Micro-
proces-
sors)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8-bit
micro-
proces-
sors, 8
bit
micro-
proces-
sors,
periph-
erals)
/Cre-
ator ()
/DOCI
NFO
pdf-
mark
Features
Description
• Maximum Input Clock Maximum Frequency Options
At VDD = 5V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 3.2MHz
- CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MHz
• Maximum Input Clock Maximum Frequency Options
At VDD = 10V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 6.4MHz
• Minimum Instruction Fetch-Execute Times
At VDD = 5V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs
- CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs
• Any Combination of Standard RAM and ROM Up to
65,536 Bytes
• 8-Bit Parallel Organization With Bidirectional Data Bus
and Multiplexed Address Bus
• 16 x 16 Matrix of Registers for Use as Multiple
Program Counters, Data Pointers, or Data Registers
• On-Chip DMA, Interrupt, and Flag Inputs
• Programmable Single-Bit Output Port
• 91 Easy-to-Use Instructions
The CDP1802 family of CMOS microprocessors are 8-bit
register oriented central processing units (CPUs) designed
for use as general purpose computing or control elements in
a wide range of stored program systems or products.
The CDP1802 types include all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili-
tate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchro-
nous interface to memories and external controllers for I/O
devices, and minimizes the cost of interface controllers. Fur-
ther, the I/O interface is capable of supporting devices oper-
ating in polled, interrupt driven, or direct memory access
modes.
The CDP1802A and CDP1802AC have a maximum input
clock frequency of 3.2MHz at VDD = 5V. The CDP1802A and
CDP1802AC are functionally identical. They differ in that the
CDP1802A has a recommended operating voltage range of
4V to 10.5V, and the CDP1802AC a recommended operat-
ing voltage range of 4V to 6.5V.
The CDP1802BC is a higher speed version of the
CDP1802AC, having a maximum input clock frequency of
5.0MHz at VDD = 5V, and a recommended operating voltage
range of 4V to 6.5V.
Ordering Information
PART NUMBER
5V - 3.2MHz
5V - 5MHz
CDP1802ACE
CDP1802BCE
CDP1802ACEX CDP1802BCEX
CDP1802ACQ CDP1802BCQ
CDP1802ACD
-
CDP1802ACDX CDP1802BCDX
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PACKAGE
PDIP
Burn-In
PLCC
SBDIP
Burn-In
PKG. NO.
E40.6
E40.6
N44.65
D40.6
D40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-3
File Number 1305.2
1 page  
CDP1802A, CDP1802AC, CDP1802BC
Static Electrical Specifications at TA = -40oC to +85oC, Except as Noted
TEST CONDITIONS
CDP1802A
PARAMETER
VCC,
VOUT
VIN
VDD
(NOTE 1)
SYMBOL (V) (V) (V) MIN TYP MAX
Quiescent Device Current IDD - - 5 - 0.1 50
- - 10 - 1 200
Output Low Drive (Sink)
Current
(Except XTAL)
IOL
0.4 0, 5
5 1.1 2.2
-
0.5 0, 10 10 2.2 4.4
-
XTAL
0.4 5
5 170 350
-
Output High Drive (Source)
Current
(Except XTAL)
IOH
4.6 0, 5
5 -0.27 -0.55
9.5 0, 10 10 -0.55 -1.1
-
-
XTAL
4.6 0
5 -125 -250
-
Output Voltage
Low Level
Output Voltage
High Level
Input Low Voltage
- 0, 5 5
-
VOL
-
0, 10
10
-
- 0, 5 5 4.9
VOH - 0, 10 10 9.9
VIL 0.5, 4.5 -
5-
0.5, 4.5 -
5, 10
-
0
0
5
10
-
-
0.1
0.1
-
-
1.5
1
1, 9 -
10 -
-
3
Input High Voltage
VIH 0.5, 4.5 -
0.5, 4.5 -
5
5, 10
3.5
4
-
-
-
-
1, 9 -
10 7
-
-
CLEAR Input Voltage
Schmitt Hysteresis
VH
-
-
5 0.4 0.5
-
-
-
5, 10 0.3
0.4
-
Input Leakage Current
IIN
Three-State Output Leakage
Current
IOUT
-
-
10 1.5
2
-
Any
Input
0, 5
0, 10
5
10
- ±10-4 ±1
- ±10-4 ±1
0, 5 0, 5
5
- ±10-4 ±1
0, 10 0, 10
10
- ±10-4 ±1
Operating Current
CDP1802A, AC
at f = 3.2MHz
IDDI - - 5 - 2 4
(Note 2)
CDP1802BC
at f = 5.0MHz
- - 5- - -
Minimum Data Retention
Voltage
VDR
VDD = VDR
- 2 2.4
Data Retention Current
IDR
VDD = 2.4V
- 0.05
-
CDP1802AC,
CDP1802BC
(NOTE 1)
MIN TYP MAX UNITS
- 1 200 µA
- - - µA
1.1 2.2
--
170 350
- mA
- mA
- µA
-0.27 -0.55 - mA
- - - mA
-125 -250 - µA
- 0 0.1 V
- - -V
4.9 5
--
-V
-V
- - 1.5 V
- - -V
- - -V
3.5 -
-V
- - -V
- - -V
0.4 0.5 - V
- - -V
- - -V
-
±10-4
±1
µA
- - - µA
-
±10-4
±1
µA
- - - µA
- 2 4 mA
- 3 6 mA
- 2 2.4 V
- 0.5 - µA
3-7
5 Page 
CDP1802A, CDP1802AC, CDP1802BC
Machine Cycle Timing Waveforms (Propagation Delays Not Shown)
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70
CLOCK
TPA
TPB
MACHINE
CYCLE
CYCLE n
CYCLE (n + 1)
CYCLE (n + 2)
MA HIGH ADD
LOW ADDRESS
HIGH ADD
LOW ADDRESS
HIGH ADD
LOW ADDRESS
FIGURE 5. GENERAL TIMING WAVEFORMS
INSTRUCTION
MRD
FETCH (S0)
MEMORY READ CYCLE
EXECUTE (S1)
NON MEMORY CYCLE
FETCH (S0)
MEMORY READ CYCLE
MWR (HIGH)
MEMORY
OUTPUT
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 6. NON-MEMORY CYCLE TIMING WAVEFORMS
EXECUTE
VALID
OUTPUT
INSTRUCTION
MRD
MWR
FETCH (S0)
MEMORY READ CYCLE
EXECUTE (S1)
MEMORY WRITE CYCLE
FETCH (S0)
MEMORY READ CYCLE
EXECUTE
MEMORY
OUTPUT
CPU OUTPUT
TO MEMORY
ALLOWABLE MEMORY ACCESS
OFF
VALID OUTPUT
VALID DATA
OFF
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 7. MEMORY WRITE CYCLE TIMING WAVEFORMS
VALID
OUTPUT
VALID
3-13
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CDP1802BC.PDF ] | |
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