CDP1806AC Datasheet PDF - Intersil Corporation
| Part Number | CDP1806AC | |
| Description | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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TM
March 1997
CDP1805AC,
CDP1806AC
CMOS 8-Bit Microprocessor with On-Chip RAM†
and Counter/Timer
Features
• Instruction Time of 3.2µs, -40oC to +85oC
• 123 Instructions - Upwards Software Compatible With
CDP1802
• BCD Arithmetic Instructions
• Low-Power IDLE Mode
• Pin Compatible With CDP1802 Except for Terminal 16
• 64K-Byte Memory Address Capability
• 64 Bytes of On-Chip RAM†
• 16 x 16 Matrix of On-Board Registers
• On-Chip Crystal or RC Controlled Oscillator
• 8-Bit Counter/Timer
n
Description
The CDP1805AC and CDP1806AC are functional and per-
formance enhancements of the CDP1802 CMOS 8-bit regis-
ter-oriented microprocessor series and are designed for use
in general-purpose applications.
The CDP1805AC hardware enhancements include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt request,
can be programmed for use in timebase, event-counting,
and pulse-duration measurement applications. The
Counter/Timer underflow output can also be directed to the
Q output terminal. The CDP1806AC hardware enhance-
ments are identical to the CDP1805AC, except the
CDP1806AC contains no on-chip RAM.
The CDP1805AC and CDP1806AC software enhancements
include 32 more instructions than the CDP1802. The 32 new
software instructions add subroutine call and return capabil-
ity, enhanced data transfer manipulation, Counter/Timer con-
trol, improved interrupt handling, single-instruction loop
counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP1805AC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of VCC with ME on the CDP1805AC and
the replacement of VCC with VDD on the CDP1806AC.
Ordering Information
CDP1805AC
CDP1805ACE
-
CDP1805ACQ
CDP1805ACD
CDP1805ACDX
CDP1806AC
CDP1806ACE
CDP1806ACEX
CDP1806ACQ
CDP1806ACD
-
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PACKAGE
Plastic DIP
Burn-In
PLCC
SBDIP
Burn-In
PKG. NO.
E40.6
N44.65
D40.6
† CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 1370.2
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CDP1805AC, CDP1806AC
Static Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued)
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
PARAMETER
VO VIN VDD
(NOTE 3)
(V) (V) (V) MIN
TYP
MAX UNITS
Input Low Voltage (BUS0 - BUS7, ME), VIL
0.5, 4.5
-
5
-
- 1.5 V
Input High Voltage (BUS0 - BUS7, ME), VIH
0.5, 4.5
-
5 3.5
-
-V
Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME)
Positive Trigger Threshold, VP
0.5, 4.5
-
5 2.2 2.9
3.6 V
Negative Trigger Threshold, VN
0.5, 4.5
-
5 0.9 1.9
2.8 V
Hysteresis, VH
0.5, 4.5
-
5 0.3 0.9
1.6 V
Input Leakage Current, IIN
- 0, 5 5 - ±0.1 ±5 µA
Three-State Output Leakage Current, IOUT
0, 5 0, 5
5
-
±0.2 ±5 µA
Input Capacitance, CIN
--- -
5 7.5 pF
Output Capacitance, COUT
- - - - 10 15 pF
Total Power Dissipation (Note 4)
Run
- -5 -
35 50 mW
Idle “00” at M (0000)
- -5 -
12 18 mW
Minimum Data Retention Voltage, VDR
Data Retention Current, IDR
NOTES:
3. Typical values are for TA = +25oC and nominal VDD.
4. External clock: f = 5MHz, t R, t F = 10ns; CL = 50pF.
VDD = VDR
VDD = 2.4
- 2 2.4 V
- 25 100 µA
Dynamic Electrical Specifications at TA = -40o to +85oC; C L = 50pF; Input tR, tF = 10ns; Input Pulse Levels = 0.1V to
VDD -0.1V; VDD = 5V, ±5%.
CDP1805AC CDP1806AC
PARAMETER
(NOTE 5)
TYP
MAX
UNITS
Propagation Delay Times
Clock to TPA, TPB, tPLH, tPHL
Clock-to-Memory High-Address Byte, tPLH, tPHL
Clock-to-Memory Low-Address Byte, tPLH, tPHL
Clock to MRD, tPLH, tPHL
Clock to MWR, tPLH, tPHL (See Note 5)
Clock to (CPU DATA to BUS), tPLH, tPHL
Clock to State Code, tPLH, tPHL
Clock to Q, tPLH, tPHL
Clock to N, tPLH, tPHL
Clock to Internal RAM Data to BUS, tPLH, tPHL
150 275
325 550
275 450
200 325
150 275
375 625
225 400
250 425
250 425
420 650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CDP1806AC.PDF Datasheet ] | |
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