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PDF CDP1823C Data sheet ( Hoja de datos )
| Número de pieza | CDP1823C | |
| Descripción | High-Reliability CMOS 128-Word x 8-Bit Static RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CDP1823C/3
March 1997
High-Reliability CMOS
128-Word x 8-Bit Static RAM
Features
• For Applications in Aerospace, Military, and Critical
Industrial Equipment
• Compatible with CDP1800-Series Microprocessors at
Maximum Speed
• Interfaces with CDP1800-Series Microprocessors
without Additional Components
• Fast Access Time
• At VDD = 5V, +25oC . . . . . . . . . . . . . . . . . . . . . . . . 275ns
• Single Voltage Supply
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory
System Expansion
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD
• Memory Retention for Standby Battery Voltage Down
to 2V at 25oC
• Latch-Up-Free Transient Radiation Tolerance
Ordering Information
PART NUMBER
PACKAGE TEMP. RANGE
(5V)
SBDIP
-55oC to +125oC CDP1823CD3
PKG. NO.
D24.6
Description
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static
random access memory. It is compatible with the CDP1802,
CDP1804, CDP1805, and CDP1806 microprocessors, and
will interface directly without additional components. The
CDP1823C has a recommended operating voltage range of
4V to 6.5V.
The CDP1823C memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip
select inputs are provided to simplify memory system
expansion. In order to enable the CDP1823C, the chip select
inputs CS2, CS3, and CS5 require a low input signal, and
the chip select inputs CS1 and CS4 require a high input
signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or tAA
(access time) after address changes.
Pinout
CDP1823C/3
(SBDIP)
TOP VIEW
BUS 0 1
BUS 1 2
BUS 2 3
BUS 3 4
BUS 4 5
BUS 5 6
BUS 6 7
BUS 7 8
CS1 9
CS2 10
CS3 11
VSS 12
24 VDD
23 A0
22 A1
21 A2
20 A3
19 A4
18 A5
17 A6
16 MWR
15 MRD
14 CS5
13 CS4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-31
File Number 2982.1
1 page  
CDP1823C/3
Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued)
LIMITS
+25oC, -55oC
+125oC
PARAMETER
SYMBOL
VDD
(V)
(NOTE 2)
MIN
MAX
(NOTE 2)
MIN
MAX
UNITS
Data Hold Time from MWR (Note 1) tDH 5 50 - 70 - ns
Chip Select Setup
tCS 5 210 - 300 - ns
NOTES:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
2. Minimum timing to allow the indicated function to occur.
ADDRESS
tAS
tWC
CS1, CS4
CS2, CS3, CS5
tCS
tAH
MWR
BUS 0-7
tWW
tDS
VALID DATA
tDH
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING WAVEFORMS
Data Retention Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
VDR
(V)
VDD
(V)
LIMITS
+25oC, -55oC
+125oC
MIN MAX MIN MAX
UNITS
Minimum Data Retention Voltage
(Note 1)
VDR - - - 2 - 2.5 V
Data Retention Quiescent Current IDD 2 - - 100 - 400 µA
Chip Deselect to Data Retention Time
tCDR
-
5 450 - 650 -
ns
Recovery to Normal Operation Time
tRC
-
5 450 - 650 -
ns
NOTE:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
6-35
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CDP1823C.PDF ] | |
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