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PDF CDP1853C Data sheet ( Hoja de datos )
| Número de pieza | CDP1853C | |
| Descripción | High-Reliability CMOS N-Bit 1 of 8 Decoder | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CDP1853C/3
March 1997
High-Reliability CMOS N-Bit 1 of 8 Decoder
Features
Description
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Micropro-
cessor
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
PACKAGE TEMP. RANGE
5V
SBDIP
-55oC to +125oC CDP1853CD3
PKG.
10V NO.
- D16.3
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose microproces-
sor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a rec-
ommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800-
series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capa-
bility for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
CLK A 1
N0 2
N1 3
OUT 0 4
OUT 1 5
OUT 2 6
OUT 3 7
VSS 8
16 VDD
15 CLK B
14 N2
13 CE
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-40
File Number 1713.2
1 page  
CDP1853/3, CDP1853C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature
Package Type D. . . .
Range
......
(TA)
....
.
.
.
.
.
.
.
.
.
.
.
.-55oC
to
+125oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Timing Diagrams
N0 - N2
OUTPUT 0 - 7
TN0
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
CE
OUTPUT 0 - 7
TEOH
TEOL
FIGURE 2B. CE TO OUTPUT DELAY TIME
MIN. CLOCK B
PULSE WIDTH
CLOCK B
TCBCB
MIN. CLOCK A
PULSE WIDTH
CLOCK A
OUTPUT 0 - 7
TCACA
TAO
OUTPUT 0 - 7
TBO
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
NOTE:
(SEE NOTE 1)
1. To measure TAO, Clock B must be tied low.
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
TPA
TPB
CE
EN
(NOTE 1)
OUTPUT
NOTE:
1. Output enabled when EN = high. Internal signal shown for refer-
ence only (see Figure 1).
FIGURE 3. TIMING DIAGRAM
A
B
C
CHIP ENABLE
VDD
OUT 0
N0 OUT 1
N1 OUT 2
N2 OUT 3
CE OUT 4
CLK B OUT 5
CLK A OUT 6
OUT 7
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
4-44
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CDP1853C.PDF ] | |
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