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CDP1854 PDF даташит

Спецификация CDP1854 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)».

Детали детали

Номер произв CDP1854
Описание High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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CDP1854 Даташит, Описание, Даташиты
March 1997
CDP1854A,
CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
Features
Description
• Two Operating Modes
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800-Series
Microprocessors without Additional Components
• Full or Half Duplex Operation
• Parity, Framing and Overrun Error Detection
• Baud Rate
- DC to 200K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 5V
- DC to 400K Bits/s at VDD . . . . . . . . . . . . . . . . . . . . 10V
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
• False Start Bit Detection
Ordering Information
The CDP1854A and CDP1854AC are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART) cir-
cuits. They are designed to provide the necessary formatting
and control for interfacing between serial and parallel data.
For example, these UARTs can be used to interface between
a peripheral or terminal with serial I/O ports and the 8-bit
CDP1800-series microprocessor parallel data bus system.
The CDP1854A is capable of full duplex operation, i.e.,
simultaneous conversion of serial input data to parallel out-
put data and parallel input data to serial output data.
The CDP1854A UART can be programmed to operate in one
of two modes by using the mode control input. When the
input is high (MODE = 1), the CDP1854A is directly compati-
ble with the CDP1800-series microprocessor system without
additional interface circuitry. When the mode input is low
(MODE = 0), the device is functionally compatible with indus-
try standard UART’s such as the TR1602A and CDP6402. It
is also pin compatible with these types, except that pin 2 is
used for the mode control input.
TEMP.
PACKAGE RANGE
5V/200K
BAUD
PDIP
-40oC to +85oC CDP1854ACE
10V/400K PKG.
BAUD
NO.
CDP1854AE E40.6
Burn-In
PLCC
SBDIP
CDP1854ACEX
-40oC to +85oC CDP1854ACQ
-40oC to +85oC CDP1854ACD
CDP1854AEX
CDP1854AQ
CDP1854AD
E40.6
N44.65
D40.6
Burn-In
CDP1854ACDX
- D40.6
The CDP1854A and the CDP1854AC are functionally identi-
cal. The CDP1854A has a recommended operating voltage
range of 4V to 10.5V, and the CDP1854AC has a recom-
mended operating voltage range of 4V to 6.5V.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-42
File Number 1193.2









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CDP1854 Даташит, Описание, Даташиты
CDP1854A, CDP1854AC
Pinouts
40 LEAD SBDIP, PDIP (MODE 0)
TOP VIEW
VDD 1
MODE (VSS) 2
VSS 3
RRD 4
R BUS 7 5
R BUS 6 6
R BUS 5 7
R BUS 4 8
R BUS 3 9
R BUS 2 10
R BUS 1 11
R BUS 0 12
PE 13
FE 14
OE 15
SFD 16
R CLOCK 17
DAR 18
DA 19
SDI 20
40 T CLOCK
39 EPE
38 WLS 1
37 WLS 2
36 SBS
35 PI
34 CRL
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
24 TSRE
23 THRL
22 THRE
21 MR
40 LEAD SBDIP, PDIP (MODE 1)
TOP VIEW
VDD 1
MODE (VDD) 2
VSS 3
CS2 4
R BUS 7 5
R BUS 6 6
R BUS 5 7
R BUS 4 8
R BUS 3 9
R BUS 2 10
R BUS 1 11
R BUS 0 12
INT 13
FE 14
PE/OE 15
RSEL 16
R CLOCK 17
TPB 18
DA 19
SDI 20
40 T CLOCK
39 CTS
38 ES
37 PS1
36 NC
35 CS3
34 RD/WR
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
24 RTS
23 CS1
22 THRE
21 CLEAR
NC = NO CONNECT
44 LEAD PLCC (Q SUFFIX)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
R BUS 6
R BUS 5
R BUS 4
R BUS 3
R BUS 2
NC
R BUS 1
R BUS 0
PE(INT)
FE
OE(PE/OE)
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
NOTE:
MODE 0(MODE 1)
PI (CS3)
CRL(RD/WR)
T BUS 7
T BUS 6
T BUS 5
NC
T BUS 4
T BUS 3
T BUS 2
T BUS 1
T BUS 0
5-43









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CDP1854 Даташит, Описание, Даташиты
CDP1854A, CDP1854AC
Block Diagram
Mode Input High (Mode = 1)
TRANSMITTER SECTION
CDP1802
INTERFACE
RECEIVER SECTION
SDO
25
PARITY
GEN
40 24 39
TRANSMITTER
TIMING &
CONTROL
34 18 16
38 37 17
RECEIVER
TIMING &
CONTROL
1, 2 = VDD
3 = VSS
21 = CLEAR
36 = NC
SHIFT
REGISTER
20
SDI
RECEIVER
HOLDING
REGISTER
TRANSMITTER
SHIFT
REGISTER
TRANSMITTER
HOLDING
REGISTER
CONTROL
REG
TRANSMITTER BUS
(26 - 33)
(SEE NOTE 1)
SELECT
LOGIC
23 4 35
INT
13
STATUS
REGISTER
22 14 15 19
(SEE NOTE 1)
MUX
THREE-STATE
DRIVERS
RECEIVER BUS
(5-12)
(SEE NOTE 1)
NOTE: 1. User Interconnect
FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)
5-44










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