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PDF CDP1872C Data sheet ( Hoja de datos )

Número de pieza CDP1872C
Descripción High-Speed 8-Bit Input and Output Ports
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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CDP1872C,
CDP1874C, CDP1875C
March 1997
High-Speed 8-Bit Input and Output Ports
Features
Description
• Parallel 8-Bit Input/Output Register with Buffered Out-
puts
• High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V
• Flexible Applications In Microprocessor Systems as
Buffers and Latches
• High Order Address-Latch Capability in CDP1800-
Series Microprocessor Systems
• Output Sink Current = 5mA (Min) at VDD = 5V
• Three-State Output - CDP1872C and CDP1874C
Ordering Information
PART
NUMBER
CDP1872CE
CDP1874CE
CDP1875CE
TEMP. RANGE PACKAGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PDIP
PDIP
PDIP
PKG.
NO.
E22.4
E22.4
E22.4
The CDP1872C, CDP1874C and CDP1875C devices are
high-speed 8-bit parallel input and output ports designed for
use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
Pinouts
CDP1872C INPUT PORT
(PDIP)
TOP VIEW
CDP1874C INPUT PORT
(PDIP)
TOP VIEW
CDP1875C OUTPUT PORT
(PDIP)
TOP VIEW
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CLOCK 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CLOCK 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CS3 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-76
File Number 1255.2

1 page




CDP1872C pdf
CDP1872C, CDP1874C, CDP1875C
MRD
TPA
MA8
•••
MA15
CDP1802
ADDRESS BUS
CLOCK
D0
D1
D2
CDP1874C D3
D4
D5
D6
D7
CSI CS2
TPB
DATA BUS
0-7
VDD
DATA BUS
CSI CLOCK
DO DI
CDP1874C
CS2
DATA IN
CS2
CS3
CDP1875C
DI DO
CS1
DATA OUT
FIGURE 6. CDP1874C USED AS AN INPUT PORT AND ADDRESS LATCH WITH CDP1875C USED AS AN OUTPUT PORT
D0 - D7
MRD
N0
N1
N2
CDP1802A
DATA BUS
Y1
Y2
Y3
Y4
Y5
A0 Y6
Y7
A1
A2
CD74HC138
DATA BUS
CS2
CLOCK
CDP1872C
CS1
DATA IN
CS2
CLOCK
CS1
CDP1872C
DATA OUT
FIGURE 7. CDP1872C USED AS AN INPUT PORT AND SELECTED BY CD74HC138
4-80

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