DataSheet26.com

CDP1874C PDF даташит

Спецификация CDP1874C изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «High-Speed 8-Bit Input and Output Ports».

Детали детали

Номер произв CDP1874C
Описание High-Speed 8-Bit Input and Output Ports
Производители Intersil Corporation
логотип Intersil Corporation логотип 

6 Pages
scroll

No Preview Available !

CDP1874C Даташит, Описание, Даташиты
CDP1872C,
CDP1874C, CDP1875C
March 1997
High-Speed 8-Bit Input and Output Ports
Features
Description
• Parallel 8-Bit Input/Output Register with Buffered Out-
puts
• High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V
• Flexible Applications In Microprocessor Systems as
Buffers and Latches
• High Order Address-Latch Capability in CDP1800-
Series Microprocessor Systems
• Output Sink Current = 5mA (Min) at VDD = 5V
• Three-State Output - CDP1872C and CDP1874C
Ordering Information
PART
NUMBER
CDP1872CE
CDP1874CE
CDP1875CE
TEMP. RANGE PACKAGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PDIP
PDIP
PDIP
PKG.
NO.
E22.4
E22.4
E22.4
The CDP1872C, CDP1874C and CDP1875C devices are
high-speed 8-bit parallel input and output ports designed for
use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
Pinouts
CDP1872C INPUT PORT
(PDIP)
TOP VIEW
CDP1874C INPUT PORT
(PDIP)
TOP VIEW
CDP1875C OUTPUT PORT
(PDIP)
TOP VIEW
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CLOCK 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CLOCK 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CS1
DI0
DO0
1
2
3
DI1 4
D01 5
DI2 6
D02 7
DI3 8
D03 9
CS3 10
VSS 11
22 VDD
21 DI7
20 D07
19 DI6
18 D06
17 DI5
16 D05
15 DI4
14 D04
13 CLR
12 CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-76
File Number 1255.2









No Preview Available !

CDP1874C Даташит, Описание, Даташиты
CDP1872C, CDP1874C, CDP1875C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
PARAMETER
LIMITS
ALL TYPES
UNITS
DC Operating-Voltage Range
4 to 6.5
V
Input Voltage Range
VSS to VDD
V
Static Electrical Specifications At TA = -40 to +85oC, VDD ±5%, Unless Otherwise Specified.
TEST CONDITIONS
LIMITS
ALL TYPES
PARAMETER
VO VIN VDD
(NOTE 1)
(V) (V) (V) MIN TYP
Quiescent Device Current
Output Low Drive (Sink)
Current
IDD -
IOL 0.4
0, 5
0, 5
5
5
- 25
5 10
Output High Drive (Source) IOH 4.6
Current
0, 5
5
-4 -7
Output Voltage Low-Level VOL - 0, 5 5 - 0
(Note 2)
Output Voltage High-Level
VOH
-
0, 5
5
4.9
5
(Note 2)
Input Low Voltage
VIL 0.5, 4.5
-
5
-
-
Input High Voltage
VIH 0.5, 4.5
-
5 3.5 -
Input Leakage Current
IIN - 0, 5 5 - -
Three-State Output Leakage
IOUT
0, 5
0, 5
5
-
-
Current (Note 3)
Input Capacitance
CIN - - - - 15
Output Capacitance (Note 3)
COUT
-
-
-
- 15
NOTES:
1. Typical values are for TA = +25oC and nominal VDD ±5%.
2. IOL = IOH = 1µA
3. For CDP1872C and CDP1874C only.
MAX
50
-
-
0.1
-
1.5
-
±1
±5
-
-
UNITS
µA
mA
mA
V
V
V
V
µA
µA
pF
pF
4-77









No Preview Available !

CDP1874C Даташит, Описание, Даташиты
CDP1872C, CDP1874C, CDP1875C
Logic Diagrams
CS1
CS2
DI
CLOCK
D
CQ
R
DO
CLR
FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) FOR CDP1872C
CS1
CS2
DI
CLOCK
D
CQ
R
DO
CLR
FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) for CDP1874C
CS1
CS2
CS3
DI D
C
Q
DO
R
CLR
FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C
Dynamic Electrical Specifications At TA = 25oC, VDD 5V, tR, tF = 10ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 150pF
LIMITS
CDP1872C, CDP1874C
PARAMETER
(NOTE 1) (NOTE 2)
MIN TYP MAX
INPUT PORT (FIGURE 4)
Output Enable
Output Disable
Clock to Data Out
Clear to Output
Data In to Data Out
Minimum Data Setup Time
Data Hold Time
Minimum Clock Pulse Width
Minimum Clear Pulse Width
NOTES:
1. Typical values are for TA = +25oC and VDD ±5%.
2. Maximum values are for TA = +85oC and VDD ±5%
tEN
tDIS
tCLO
tCRO
tDIO
tDSU
tDH
tCL
tCR
-
-
-
-
-
-
-
-
-
45 90
45 90
45 90
80 160
50 85
10 30
10 30
30 60
30 60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-78










Скачать PDF:

[ CDP1874C.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
CDP1874CHigh-Speed 8-Bit Input and Output PortsGE
GE
CDP1874CHigh-Speed 8-Bit Input and Output PortsIntersil Corporation
Intersil Corporation

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск