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PDF CBTL04083A Data sheet ( Hoja de datos )
| Número de pieza | CBTL04083A | |
| Descripción | 2 : 1 multiplexer/demultiplexer switch | |
| Fabricantes | NXP Semiconductors | |
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CBTL04083A; CBTL04083B
3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer
switch for PCI Express Gen3
Rev. 4 — 25 June 2012
Product data sheet
1. General description
CBTL04083A/B is a 4 differential channel, 2-to-1 multiplexer/demultiplexer switch for
PCI Express Generation 3 (Gen3) applications. The CBTL04083A/B can switch four
differential signals to one of two locations. Using a unique design technique, NXP has
minimized the impedance of the switch such that the attenuation observed through the
switch is negligible, and also minimized the channel-to-channel skew as well as
channel-to-channel crosstalk, as required by the high-speed serial interface.
CBTL04083A/B allows expansion of existing high speed ports for extremely low power.
The device's pin out are optimized to match different application layouts. CBTL04083A
has input and output pins on the opposite of the package, and is suitable for edge
connector(s) with different signal sources on the motherboard. CBTL04083B has outputs
on both sides of the package, and the device can be placed between two connectors to
multiplex differential signals from a controller. Please refer to Section 8 for layout
examples.
2. Features and benefits
4 differential channel, 2 : 1 multiplexer/demultiplexer
High-speed signal switching for 8.0 Gbit/s PCIe Gen3 speed
Low intra-pair skew: 5 ps typical
Low inter-pair skew: 35 ps maximum
High bandwidth:
−3 dB at 8.3 GHz for CBTL04083A
−3 dB at 8.0 GHz for CBTL04083B
Low crosstalk: −29 dB at 4 GHz
Low insertion loss
−0.5 dB at 100 MHz
−1.3 dB at 4 GHz
Low off-state isolation: −20 dB at 4 GHz
Low return loss: −14 dB at 4 GHz
VDD operating range: 3.3 V ± 10 %
Dual shutdown pins for channel 0/1 and 2/3 independently to minimize power
consumption
ESD tolerance:
2000 V HBM
1000 V CDM
HVQFN42 package
1 page  
NXP Semiconductors
CBTL04083A; CBTL04083B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3
Table 2.
Symbol
B0_P
B0_N
B1_P
B1_N
B2_P
B2_N
B3_P
B3_N
C0_P
C0_N
C1_P
C1_N
C2_P
C2_N
C3_P
C3_N
SEL
XSD01
XSD23
VDD
GND[1]
Pin description …continued
Pin Type
CBTL04083A CBTL04083B
38 37 I/O
37 36 I/O
36 33 I/O
35 32 I/O
29 28 I/O
28 27 I/O
27 24 I/O
26 23 I/O
34 3
I/O
33 4
I/O
32 7
I/O
31 8
I/O
25 12 I/O
24 13 I/O
23 16 I/O
22 17 I/O
9 30 CMOS
single-ended input
41 40 CMOS
single-ended input
19 20 CMOS
single-ended input
5, 8, 13, 18,
20, 30, 40, 42
1, 4, 10, 14,
17, 21, 39,
center pad
9, 19, 21, 26, power
31, 34, 39, 41
18, 22, 25, ground
29, 35, 38, 42,
center pad
Description
channel 0, port B differential signal input/output
channel 1, port B differential signal input/output
channel 2, port B differential signal input/output
channel 3, port B differential signal input/output
channel 0, port C differential signal input/output
channel 1, port C differential signal input/output
channel 2, port C differential signal input/output
channel 3, port C differential signal input/output
operation mode select
SEL = LOW: A → B
SEL = HIGH: A → C
Shutdown pin; should be driven LOW or connected to
GND for normal operation. When HIGH, channel 0 and
channel 1 are switched off (non-conducting
high-impedance state), and supply current consumption
is minimized.
Shutdown pin; should be driven LOW or connected to
GND for normal operation. When HIGH, channel 2 and
channel 3 are switched off (non-conducting
high-impedance state), and supply current consumption
is minimized.
positive supply voltage, 3.3 V ± 10 %
supply ground
[1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the
exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through
the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL04083A_CBTL04083B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
13. Test information
CBTL04083A; CBTL04083B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3
PULSE
GENERATOR
VIC
VDD
DUT
VO
RT
RL
200 Ω
2 × VIC
open
GND
CL RL
50 pF 200 Ω
002aag014
Fig 5.
CL = load capacitance; includes jig and probe capacitance.
RT = termination resistance; should be equal to Zo of the pulse generator.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 5 MHz;
Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns.
Test circuitry for switching times
PORT 1
4-PORT, 20 GHz
NETWORK ANALYZER
PORT 2
PORT 3
PORT 4
Fig 6. Test circuit
Table 9. Test data
Test
tPLZ, tPZL (output on B side)
tPHZ, tPZH (output on B side)
tPD
Load
CL
50 pF
50 pF
-
DUT
002aae655
RL
200 Ω
200 Ω
200 Ω
Switch
2 × VIC
GND
open
CBTL04083A_CBTL04083B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CBTL04083A.PDF ] | |
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