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PDF CBTL04DP211 Data sheet ( Hoja de datos )
| Número de pieza | CBTL04DP211 | |
| Descripción | DisplayPort 2 : 1 multiplexer | |
| Fabricantes | NXP Semiconductors | |
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CBTL04DP211
DisplayPort 2 : 1 multiplexer
Rev. 2 — 13 April 2012
Product data sheet
1. General description
CBTL04DP211 is an (Embedded) DisplayPort multiplexer for DisplayPort v1.1a switching
and multiplexing applications on PC platforms. It is capable of 1 : 2 switching or
2 : 1 multiplexing of 2-lane DisplayPort Main Link signals, using high-bandwidth pass-gate
technology. Also, it can switch/multiplex Hot Plug Detect (HPD) signal and AUX signals,
for a total of four channels on the display side.
To facilitate DisplayPort switching/multiplexing scheme on PC platforms suitably,
CBTL04DP211 provides two separate selection pins (GPU_SEL, AUX_SEL). The
selection pin GPU_SEL performs switching from one Main Link to another Main Link. HPD
signals will also be switched using the same selection pin. A separate select pin
(AUX_SEL) provides additional selection between two AUX channels such that the AUX
channel selection is independent of the Main Link and HPD signal selection.
A typical application of CBTL04DP211 is on motherboards where one of two GPU/CPU
display sources needs to be selected to connect to a DisplayPort sink device or connector.
A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to
the non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL04DP211 can also be used in the reverse topology, e.g., to connect
one DisplayPort source device to one of two DisplayPort sink devices or connectors.
2. Features and benefits
Supports DisplayPort v1.1a: 1.62 Gbit/s, 2.7 Gbit/s
Supports Embedded DisplayPort v1.2: 1.62 Gbit/s, 2.7 Gbit/s
Supports 1-lane, 2-lane Main Link operation
1 : 2 switching or 2 : 1 multiplexing of DisplayPort Main Link signals
2 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
Main Link signals
1 channel with 2 : 1 multiplexing/switching for AUX signals
1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Single 3.3 V power supply
Very low operation current of 0.2 mA typical
ESD 8 kV HBM, 1 kV CDM
ESD 2 kV HBM, 500 V CDM for control pins
Available in 3 mm × 6 mm, 0.4 mm pitch HVQFN32 package
1 page  
NXP Semiconductors
CBTL04DP211
DisplayPort 2 : 1 multiplexer
Table 2.
Symbol
OUT_0+
OUT_0−
OUT_1+
OUT_1−
AUX1+
AUX1−
AUX2+
AUX2−
AUX+
AUX−
HPD_1
HPD_2
HPD_IN
VDD
GND[1]
n.c.
Pin description …continued
Pin Type
1 differential I/O
2 differential I/O
4 differential I/O
5 differential I/O
19 differential I/O
18 differential I/O
15 differential I/O
14 differential I/O
6 differential I/O
7 differential I/O
17 single-ended I/O
13 single-ended I/O
8 single-ended I/O
3, 9, 12, 16, power supply
20, 29
21, 28,
ground
center pad
11 -
Description
Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals.
High-speed differential pair for AUX signals,
path 1.
High-speed differential pair for AUX signals,
path 2.
High-speed differential pair for AUX signals.
Single-ended channel for the HPD signal, path 1.
Single-ended channel for the HPD signal, path 2.
Single-ended channel for the HPD signal.
3.3 V power supply.
Ground.
Not connected. This pin is not connected to any
signal internally.
[1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL04DP211
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 April 2012
© NXP B.V. 2012. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
12. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; 3 x 6 x 0.85 mm
terminal 1
index area
D
BA
CBTL04DP211
DisplayPort 2 : 1 multiplexer
SOT1185-1
EA
A1
detail X
c
e1
e
12
L
11
b
16
v CAB
wC
17
e
Eh e2
y1 C
C
y
1 27
terminal 1
index area
32 28
Dh
X
Dimensions
0 2.5 5 mm
scale
Unit
A(1) A1 b
c D(1) Dh E(1) Eh e e1 e2
max 1.00 0.05 0.25
3.1 1.9 6.1 4.9
mm nom 0.85 0.02 0.20 0.2 3.0 1.8 6.0 4.8 0.4 1.6
min 0.80 0.00 0.15
2.9 1.7 5.9 4.7
4
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
L v w y y1
0.4
0.3 0.07 0.05 0.08 0.1
0.2
European
projection
SOT1185-1
---
---
---
Fig 4. Package outline SOT1185-1 (HVQFN32)
CBTL04DP211
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 April 2012
sot1185-1_po
Issue date
10-07-26
10-08-09
© NXP B.V. 2012. All rights reserved.
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