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PDF CF5705CF Data sheet ( Hoja de datos )
| Número de pieza | CF5705CF | |
| Descripción | Analog Watch Stepping Motor Driver | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CF5705CF (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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NIPPON PRECISION CIRCUITS INC.
CF5705 series
Analog Watch Stepping Motor Driver
OVERVIEW
The CF5705 series is a low-current analog watch stepping motor driver CMOS IC with built-in 32.768 kHz
crystal oscillator circuit.
FEATURES
s 32.768 kHz crystal oscillator circuit
CG and CD built-in
s −3.6 to −1.2 V operating supply voltage range
s Operating current consumption
• VSS = –1.55V, CD = 16pF: 250 nA (max)
• VSS = –2.8V, CD = 26pF: 1000 nA (max)
Note: Current consumption depends on the built-in capacitor.
s Reset function
4 Hz and subsequent frequency dividers are reset
SERIES LINEUP
Pad coordinates
Motor
Version
CF5705AA
CF5705BC
CF5705AD
CF5705AE
CF5705CF
CF5705CG
1234
XT XTN RESET VSS
VSS RESET XT XTN
XT XTN RESET VSS
XT XTN RESET VSS
VSS TEST XTN XT
VSS TEST XTN XT
5
TEST
VDD
TEST
TEST
VDD
VDD
6
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
Cycle Pulse
7 8 (Tcy/2) (Tpw)
sec sec
OUT1 VDD 1 4.9m
OUT1 TEST 250m 23.4m
OUT1 VDD
1 23.4m
OUT1 VDD 20 5.9m
OUT1 RESET 1
4.9m
OUT1 RESET 1
3.9m
Test
(Tcy)
sec
125m
125m
125m
125m
62.5m
62.5m
1. Parasitic capacitance is included. Parasitic capacitance: CG = CD = 4pF
Built-in
capacitor1
CG CD
pF pF
4 16
4 26
4 30
4 16
4 16
4 16
PART NUMBER GUIDE
CF5705
Function(Motor, Built-in capacitor)
Pad coordinate
ORDERING INFORMATION
Device
C F 5 7 0 5 ××
Package
Chip form
NIPPON PRECISION CIRCUITS—1
1 page  
FUNCTIONAL DESCRIPTION
Motor Output Waveform
TPW
CF5705 series
OUT1
OUT2
TPW
TCY/2
TCY/2
VDD
VSS
VDD
VSS
The motor output waveform cycle time and output pulsewidth are set by mask option.
Reset Function
RESET
(open)
T < TON
TPW
T > TON
OUT1
OUT2
TCY/2
TCY/2
TD
VDD
VSS
VDD
VSS
VDD
VSS
Reset operation
A reset operation occurs when RESET is held HIGH
(VDD) for a period of 93.75 ms or greater, otherwise
the reset is ignored. When the reset pulse is valid, the
4 Hz and subsequent frequency dividers are reset.
Reset Release
When the reset is released, the first output pulse
occurs on the output pin opposite the output pin
where the preceding motor drive output pulse
occurred; first pulse occurs on OUT1 if previous
motor drive pulse occurred on OUT2, and vice versa.
A delay of TCY/2 − 0.125 to TCY/2 takes place from
when reset is released until the first output pulse
occurs.
NIPPON PRECISION CIRCUITS—5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CF5705CF.PDF ] | |
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