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CGS3318M PDF даташит

Спецификация CGS3318M изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «CMOS Crystal Clock Generators».

Детали детали

Номер произв CGS3318M
Описание CMOS Crystal Clock Generators
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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CGS3318M Даташит, Описание, Даташиты
September 1995
Revised March 1999
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 •
CGS3316 • CGS3317 • CGS3318 • CGS3319
CMOS Crystal Clock Generators
General Description
The CGS3311, CGS3312, CGS3313, CGS3314,
CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319
devices are designed for Clock Generation and Support
(CGS) applications up to 110 MHz. The CGS331x series of
devices are crystal controlled CMOS oscillators requiring a
minimum of external components. The 331x devices pro-
vide selectable output divide ratio (and selectable crystal
drive level). The circuit is designed to operate over a wide
frequency range using fundamental model or overtone
crystals.
Features
s Fairchild’s CGS family of devices for high frequency
clock source applications
s Crystal frequency operation range:
fundamental: 10 MHz to 100 MHz typical
3rd or 5th overtone: 10 MHz to 85 MHz
s Programmable oscillator drive
s Selectable fast output edge rates
s Output symmetry circuit to adjust 50% duty cycle point
between CMOS and TTL levels
s Output current drive of 48 mA for IOL/IOH
s FACTCMOS output levels
s Output has high speed short circuit protection
s Basic oscillator type: Pierce
s Hysteresis inputs to improve noise margin
Ordering Code:
Order Number Package Number Package Description
CGS3311M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3312M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3313M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3314M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3315M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3316M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3317M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3318M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3319M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010980.prf
www.fairchildsemi.com









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CGS3318M Даташит, Описание, Даташиты
Connection Diagrams
(A) 3311
(B)3312
(C) 3313
(E) 3315
(F) 3316
(G) 3317
(D) 3314
(H) 3318
(I) 3319
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CGS3318M Даташит, Описание, Даташиты
Truth Tables
Division Selection
DIVB DIVA OEL
F 0/F X
1 0/F 0
0 0/F 0
F1 0
110
010
XX1
XXX
OEH
X
1
1
1
1
1
X
0
Divider Output
Divide-by 1
Divide-by 2
Divide-by 4
Divide-by 8
Divide-by 16
Divide-by 32
Output Reset HIGH
at Re-enable
Output Reset HIGH
at Re-enable
Note: Actual value of the floating OSC_DR and DIVB input is VCC/2
Pin Descriptions
Rise and Fall Time Selection
OSC_DR DIV TRF Rise/Fall Time (ns)
F N 0/F 2
F N 1 less than 2
F Y 0/F 4
F Y1 2
0,1 X 0/F 4
0,1 X 1 2
Drive Selection
OSC_DR
0
1
F
Drive
Low
Medium
High
Note: Where “F” indicates floating the input.
Note: Pin out varies for each device.
OSC_IN Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEL
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
TRF
OSC_DR 3 Level input pin that selects Oscillator Drive OUT
Level
DIVA
Input used to select Binary Divide-by Option. OSCLO_1
This pin has CMOS compatible input levels.
OEH
Active HIGH 3-STATE enable pin. This pin pulls OSCLO_2
to a high value when left floating and 3-STATEs
the output when forced low. This pin has TTL
compatible input levels.
VCC
GND
Active LOW 3-STATE enable pin. This pin pulls
to a low value when left floating and 3-STATE
the output when forced HIGH. This pin has TTL
compatible input levels.
Rise and Fall time override pin. Available only
for die form.
This pin is the main clock output on the device.
The Oscillator LOW pin is the ground for the
Oscillator.
This pin is the same signal as OSCLO_1. It has
been provided as an alternate connection for
OSCLO_1 for hybrid assemblies.
The power pin for the chip.
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
Functional Table
Summary of Device Options
Device
3311
3312
3313
3314
3315
3316
3317
3318
3319
Divide
1, 2, 4
1, 2, 4
8, 16, 32
8, 16, 32
1, 2, 4
4
32
1, 2, 4
1, 2, 4
Enable
OEH
OEH
OEH
OEH
OEL
OEH
OEH
OEH
OEL
Drive
L, M, H
H
H
L, M, H
H
H
H
H
L, M, H
Output Rise/
Fall Time (ns)
2, 4
2, 4
4
4
1, 2
4
4
1, 2
2, 4
Each drive has one output with the choices of selecting frequency divide,
output enable, crystal drive and output rise and fall time. Crystal drive
options are:
L = LOW Drive
M = MEDIUM Drive
H = HIGH Drive
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Номер в каталогеОписаниеПроизводители
CGS3318MCMOS Crystal Clock GeneratorsFairchild Semiconductor
Fairchild Semiconductor

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