|
|
PDF CGS410 Data sheet ( Hoja de datos )
| Número de pieza | CGS410 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CGS410 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
September 1995
CGS410
Programmable Clock Generator
General Description
The CGS410 is a programmable clock generator which pro-
duces a variable frequency clock output for use in graphics
disk drives and clock synchronizing applications The
CGS410 produces output clocks in CMOS and differential
formats The user is able to program the differential output
levels to best suit the levels of the interfacing device A
common configuration allows PCLK to emulate positive ECL
logic levels eliminating the need for TTL to ECL translation
The CGS410 is referenced off the XTLIN input which can be
configured for either external crystal or external oscillator
support All internal frequency generation is referenced from
the XTLIN input The CGS410 can also be driven by
EXTCLK as desired EXTCLK may serve as the source from
a fixed clock (for passthru mode) or as an external VCO
input
The CGS410 contains three internal user-selectable low
pass filters (LPFs) A fourth option allows for the use of an
external LPF configuration Use of the internal filters greatly
simplifies layout reduces board real estate and minimizes
part count A programmable polarity charge pump allows
the user to optimize the optional external LPF circuitry
The primary loop structure of the CGS410 consists of pro-
grammable N and R dividers Both are contiguous N can be
any value between 2 and 16383 and R can be any value
between 1 and 1023 Additional dividers of the internal
VCO allow individual programmability for the PCLK
CMOS PCLK and LCLK outputs
An additional advantage of the CGS410 is its ability to per-
form smooth glitch-free clock output changes as the user
selects passthru clock sources or changes the VCO
frequency A real-time synchronous load clock enable
(LCLK EN) control input allows for the enabling and dis-
abling of the LCLK output This is suitable for applications
which require the removal of an active LCLK during the
blanking portion of a screen refresh
On power-up the XTLIN frequency is internally divided by
two and routed to the PCLK outputs providing a known
power-up output frequency with a 50% duty cycle The
CGS410 is programmed by a serial stream of data A serial
bit read can verify the contents of the register
Features
Y Fully programmable frequency generator
Y Provides frequencies to 135 MHz
Y Configurable high-speed complementary clock outputs
Y CMOS output clocks
Y Glitch-free transitions for clock changes
Y Powers up in a known state
Y Single supply (a5V) operation
Y Low current draw ideal for battery applications
Y Read write control register
Y Internal VCO and loop filters
Connection Diagram
TL F 11919 – 1
Important Note This device is sensitive to noise on certain pins especially FREQCTL FILTER AVDD and AGND Special care must be taken with board
layout for optimum performance
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11919
RRD-B30M115 Printed in U S A
1 page  
3 0 Circuit Operation
The CGS410 programmable clock generator uses a crystal
oscillator as a frequency reference to generate clock sig-
nals for video applications such as display systems or disk
drive constant density recording The reference may come
from any source as long as input specifications are main-
tained Both single-ended (CMOS) and differential clock
outputs are generated Both clock outputs are synchronized
to simplify system timing A unique combination of internal
functions (such as the VCO the crystal oscillator a phase
comparator various programmable counters and a read-
able 47-bit serial control register) allows for versatility and
ease of design
3 1 INTERNAL VCO OPERATION
No external VCO inductor or capacitor components are re-
quired for operation simplifying PC board layout require-
ments P counter programmability is contiguous from 1 to
16 although a 50% duty cycle will be created only if the P
modulus is an even number or if the P modulus is 1
3 1 1 VCO Tuning Characteristics
The CGS410 VCO requires an input voltage to set the prop-
er operating frequency The input voltage is the direct result
of charge sourced or sinked off the LPF network The func-
tion of the LPF is to convert the charge to voltage (see
‘‘Loop Filter Characteristics’’) The VCO requires the input
voltage to be set in the linear portion of the input range The
VCO output frequency is a function of the VCO gain (FVCO)
and the range of the input voltage
Normal or linear VCO operation will place the input voltage
range from AVDD 3 (the lowest frequency response) to ap-
proximately AVDD b 1 5V (the highest frequency re-
sponse) The linear operating range is illustrated in Figure
3-1 with VCO output frequency (FVCO) expressed as a volt-
age filter input (VFILTER)
show an output waveform well within the XVDD and XGND
boundary conditions The elements forming the crystal tank
should be low-leakage devices Capacitor values (per crys-
tal leg) will typically fall within the range of 10 pF – 40 pF
The crystal oscillator divide-by-2 output may be directed to
appear at the clock outputs depending on the state of the 3
to 1 MUX On power up both differential and CMOS PCLK
outputs will reflect half the oscillator frequency input The
XTLIN pin can be driven from a variety of sources including
ECL TTL or CMOS logic Attach a coupling capacitor into
the XTLIN pin when using a TTL or small-signal source
(such as ECL) Please see application diagrams for details
The CGS410 may be used to genlock to an external clock
source
3 3 PHASE COMPARATOR OPERATION
The phase comparator compares the difference in clock
edges between the internal N and R counter outputs The
difference results as either a charge source (pump-up) or
charge sink (pump-down) The amount of charge is directly
proportional to the phase difference (see Figure 3-2 ) The
phase comparator controls the VCO by comparing the
phase of a derived signal from a known accurate reference
source such as a crystal or an external reference signal In
genlocking situations the reference source may be a con-
stant stream of pulses such as an external HSYNC
TL F 11919 – 3
FIGURE 3-1 Linear Operating Range
Applying an input voltage beyond the intended range will
force the VCO to rail high or low Input voltages which ex-
ceed AVDD or go negative with respect to AGND can dam-
age the CGS410
3 2 CRYSTAL OSCILLATOR OPERATION
The XTLIN and XTLOUT pins are used in conjunction with
an external crystal two capacitors and two resistors to form
an external oscillator tank circuit The crystal should be a
fundamental parallel mode type XTLOUT serves as the
driving source to the crystal Consideration should be given
to avoiding crystal overdrive situations XTLOUT should
TL F 11919 – 4
FIGURE 3-2 Phase Comparator Charge Pump
The VCO-derived signal is divided by N and applied to one
phase comparator input The R divider output serves as the
other phase comparator reference input The comparator
functions as a three-state machine providing a pump-up
state when R leads N and a pump-down state when N
leads R This situation exists only when there is a difference
between the two input edges The VCO frequency is then
increased or decreased in the closed loop system At all
other times the phase comparator is in a tri-state condition
The direction and amount of charge on the FILTER pin is
proportional to the difference in the phase comparator input
edges The charge flow is made up of correction pulses
The resulting correction pulses are converted to a voltage
as dictated by the LPF network Selection of LPF compo-
nents characterizes the resulting voltage and phase re-
sponse
5
5 Page 
3 0 Circuit Operation (Continued)
the resistive termination is normally set to provide a voltage
of 3V This is readily accomplished with R1 e 220 and
R2 e 330 With the control register differential level (bit 1)
equal to 0 the output VOL e BVDD 0 642V or 3 21V at
BVDD e 5V The VOH is typically BVDD 0 824V or 4 12V
at BVDD e 5V In this example
IO(MAX) e (VOH b VL) RL
e (4 12 b 3) 132
e 9 5 mA
Generation of VOH requires the maximum IO Since the
CGS410 can provide up to 21 mA of output source for VOH
this is well within driving specifications
TL F 11919 – 12
FIGURE 3-10 Typical Termination (Bit 1 e 0)
Other factors which influence the differential output re-
sponse include the characteristic impedance of the line (ZL)
and capacitive loads The characteristic impedance of the
‘‘stripline’’ connecting the CGS410 output to the destination
device input should match the Thevenin equivalent of the
line termination to assure maximum power transfer glitch-
free clock outputs and reduced EMI
Capacitive loading will affect the rise and fall times of the
output waveform The current required is i C V T
Figure 3-11 indicates typical loading parameters used for
driving differential output capacitive loads for frequencies
from 25 MHz to 200 MHz with a 1V differential voltage
swing In addition the resulting graph bases the voltage
slew rate (v t) for 1 10 of the operating frequency period
The graph illustrates the fact that as the output frequency
and capacitance increase the amount of source current
must also increase to maintain reasonable slew rates
TL F 11919 – 13
FIGURE 3-11 PCLK PCLKB Load vs Frequency
CMOS PCLK drive requirements vary greatly from those of
the PCLK differential counterparts because the output buff-
er size and the output impedance are higher Best perform-
ance is usually obtained by placing a series resistor on the
output and then driving to the receiving device Selection of
the resistor is best obtained on an empirical basis Normally
resistor sizes starting in the 10X –80X range provide a good
start Figure 3-10 shows a typical termination scheme for
60 – 70 board impedance
3 10 SYSTEM INTERFACE CONSIDERATIONS
The CGS410 data bus can be managed by a wide variety of
controllers If a serial data source is not available from the
controller external serializing circuitry or slight bus modifi-
cation may be required
Figure 3-12 illustrates a generic hardware system imple-
mentation where the CGS410 control signals are qualified
through a memory map In this example the CGS410 is
mapped into two address locations This particular mapping
scheme allows
1) typical read write operations to execute through one
mapped port
2) transfer operations to execute through the second
mapped port (see Figure 3-12)
Depending on the system configuration CGS410 control
signals such as R WB may be connected directiy to a qual-
ified CPU strobe R WE In this example the system bus
data line zero D 0 serves as the DATA port of the CGS410
The control signal EN may be derived from address decode
select logic and can maintain any state during non-CGS410
accesses
The control signal CSB requires the greatest attention be-
cause it is the CGS410’s clocking agent Care must be tak-
en to ensure that no activity takes place on this input during
non-CGS410 accesses Note that when this input is
strobed all control and data present at the CGS410 must
conform to the respective rising and falling edges of this
signal as specified in the timing diagrams in this data sheet
CSB may be generated from a variety of system sources A
qualified CPU WAIT may serve as one source Other timing
requirements may need a timing generator (such as a two-
state machine) to generate CSB
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CGS410.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CGS410 | Programmable Clock Generator | National Semiconductor |
| CGS412T250V4L | High-Cap Screw Terminal Aluminum Electrolytic Capacitor |  CDE |
| CGS412T250V5L | High-Cap Screw Terminal Aluminum Electrolytic Capacitor | CDE |
| CGS412T300W4C | High-Cap Screw Terminal Aluminum Electrolytic Capacitor | CDE |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |