PDF CGS701ATV Data sheet ( Hoja de datos )

Número de pieza	CGS701ATV
Descripción	Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
Fabricantes	National Semiconductor
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December 1995 CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General Description CGS701A is an off the shelf clock driver specifically de- signed for today’s high speed designs It provides low skew outputs which are produced at different frequencies from three fixed input references The XTALIN input pin is de- signed to be driven from a 25 MHz–40 MHz crystal oscilla- tor The PLL using a charge pump and an internal loop filter multiplies this input frequency to create a maximum output frequency of four times the input The device includes a TRI-STATE control pin to disable the outputs This feature allows for low frequency functional testing and debugging Also included is an EXTSEL pin to allow testing the chip via an external source The EXTSEL pin once set to high caus- es the External-Clock MUX to change its input from the output of the VCO and Counter to the external clock signal provided via SKWTST input pin (continued) Features Y Guaranteed 400 ps pin-to-pin skew (tOSHL and tOSLH) on 1X outputs Y Pentium and PowerPCTM compatible Y g300 ps propagation delay Y Output buffer of eight drivers for large fanout Y 25 MHz – 160 MHz output frequency range Y Outputs operating at 4X 2X 1X of the reference fre- quency for multifrequency bus applications Y Selectable output frequency Y Internal loop filter to reduce noise and jitter Y Separate analog and digital VCC and ground pins Y Low frequency test mode by disabling the PLL Y Implemented on National’s Core CMOS process Y Symmetric output current drive a30 b30 mA IOL IOH Y Industrial temperature of b40 C to a85 C Y 28-pin PLCC for optimum skew performance Y Guaranteed 2k volts ESD protection Connection Diagram Pin Assignment for PLCC TL F 11920 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation Pentium is a registered trademark of Intel Corporation PowerPCTM is a trademark of International Business Machines Corporation Pin Description PLCC Package Pin Name Description 1 VCC 2 FBK IN Digital VCC Feedback Input Pin 3 CLK4 4X Clock Output 4 VCC 5 XTALIN Digital VCC Crystal Oscillator Input 6 GND Digital Ground 7 FBK OUT Feedback Output Pin 8 VCC 9 CLK1 l Digital VCC 1X Clock Output 10 GND Digital Ground 11 CLK1 2 1X Clock Output 12 TRI-STATE Output TRI-STATE Control 13 SKWTST Skew Testing Pin 14 CLK1 3 1X Clock Output 15 GND Digital Ground 16 CLK1 4 1X Clock Output 17 VCC 18 SKWSEL Digital VCC Skew Test Selector Pin 19 GNDA Analog Ground 20 VCCA 21 EXTSEL Analog VCC External Clock MUX Selector 22 GND Digital Ground 23 CLK1 5 1X Clock Output 24 VCC 25 CLK1 0 Digital VCC 1X Clock Output 26 CLK1SEL CLK1 Multiplier Selector 27 GND Digital Ground 28 CLK2 2X Clock Output C1996 National Semiconductor Corporation TL F 11920 RRD-B30M106 Printed in U S A http www national com 1 page CGS701A AC Electrical Characteristics Over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C Symbol Parameter VCC e 4 5V – 5 5V FIN e 25 to 40 MHz T e 0 C to a70 C CL e Circuit 1 RL e Circuit 1 Min Typ Max Units Notes trise Output Rise CLK4 0 8V to 2 6V CLK2 1 0V to VCC b 1 0V CLK1 1 0V to VCC b 1 0V All 0 8V to 2 0V (Note 1 7) 2 0 ns 15 tfall Output Fall CLK4 2 6V to 0 8V CLK2 VCC b 1 0V to 1 0V CLK1 VCC b 1 0V to 1 0V All 0 8V to 2 0V (Note 1 7) 2 0 ns 15 tSKEW Maximum Edge-to- Edge Output Skew a to a Edges a to a Edges a to a Edges CLK1 CLK1 CLK1 CLK4 CLK2 CLK4 400 1000 1000 (Note 2 7) ps tLOCK tCYCLE Time to Lock the Output to the Synch Input Output Duty Cycle CLK1 Outputs CLK2 Output CLK4 Output 49 49 35 20 100 ms 51 (Note 3 7) 51 % 65 JLT Output Jitter (Long Term) 0 3 ns (Note 4 7) tPD Propogation Delay from XTALIN to FBKOUT b0 3 a0 3 ns (Notes 2 4 5 6 7) FMIN Minimum XTALIN Frequency 15 MHz FMAX Maximum XTALIN Frequency 43 MHz Note 1 trise and tfall parameters are measured at the pin of the device Note 2 Skew is measured at 50% of VCC for CLK1 and CLK2 while it is being measured at 1 4V for CLK4 Limits are guaranteed by design Note 3 Output duty cycle is measured at VDD 2 for CLK1 and CLK2 while it is being measured at 1 4V for CLK4 Limits are guaranteed by design Note 4 Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles It is also measured at output levels of VCC 2 Refer to Figure 3 for further explanation Note 5 Measured from the ref input to any output pin The length of the feedback and XTALIN traces will impact this delay time Note 6 This parameter includes pin-to-pin skew longterm jitter over 1000 cycles part-to-part variation as well as propagation delay thru the device Note 7 The GNDA pins of the 701 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for the VCCA pin Circuit 1 Test Circuit TL F 11920 – 4 5 http www national com 5 Page

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