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PDF CGS702V Data sheet ( Hoja de datos )
| Número de pieza | CGS702V | |
| Descripción | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1995
CGS702V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
with Improved EMI
General Description
The CGS702 is an off-the-shelf clock driver specifically de-
signed for today’s high speed processors It provides low
skew outputs which are produced at different frequencies
from three fixed input references The CGS702 is a reduced
EMI version of the CGS700 The XTALIN input pin is de-
signed to be driven from three distinct crystal oscillators run-
ning at 25 MHz 33 MHz or 40 MHz
The PLL using a charge pump and an internal loop filter
multiplies this input frequency to create a maximum output
frequency of four times the input
The device includes a TRI-STATE control pin to disable
the outputs while the PLL is still in lock This function allows
testing the board without having to wait to acquire the lock
once the testing is complete
(Continued)
Features
Y Reduced EMI compared to CGS700 (refer to EMI
characteristics)
Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL
and TOSLH) on 1x outputs
Y PentiumTM and PowerPCTM compatible
Y Output buffer of nine drivers for large fanout
Y 25 MHz – 160 MHz output frequency range
Y Outputs operating at 4x 2x 1x of the reference
frequency for multi-frequency bus applications
Y Selectable output frequency
Y Internal loop filter to reduce noise and jitter
Y Separate Analog and digital VCC and Ground pins
Y Low frequency test mode by disabling the PLL
Y Implemented on National’s Core CMOS process
Y Symmetric output current drive
a30 mA b30 mA IOL IOH
Y 28-pin PCC for optimum skew performance
Y Guaranteed 2 kV ESD protection
Connection Diagram
Pin Assignment for PLCC
TL F 12386 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PentiumTM is a trademark of Intel Corporation
PowerPCTM is a trademark of International Business Machines Corporation
Pin Description
PLCC Package
Pin Name
Description
1 VCC
2 SKWSEL
Digital VCC
Skew Test Selector Pin
3 CLK4
4x Clock Output
4 VCC
5 XTALIN
Digital VCC
Crystal Oscillator Input
6 GND
Digital Ground
7 CLK1 0
1x Clock Output
8 VCC
9 CLK1 1
Digital VCC
1x Clock Output
10 GND
Digital Ground
11 CLK1 2
1x Clock Output
12 TRI-STATE Output TRI-STATE Control
13 SKWTST
Skew Testing Pin
14 CLK1 3
1x Clock Output
15 GND
Digital Ground
16 CLK1 4
1x Clock Output
17 VCC
18 EXTCLK
Digital VCC
External Test Clock
19 GNDA
Analog Ground
20 VCCA
21 EXTSEL
Analog VCC
External Clock MUX Selector
22 GND
Digital Ground
23 CLK1 5
1x Clock Output
24 VCC
25 CLK1 6
Digital VCC
1x Clock Output
26 CLK1SEL
CLK1 Multiplier Selector
27 GND
Digital Ground
28 CLK2
2x Clock Output
C1995 National Semiconductor Corporation TL F 12386
RRD-B30M105 Printed in U S A
1 page  
CGS702 AC Electrical Characteristics
over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C
Symbol
Parameter
VCC e 4 5V to 5 5V
fIN e 25 MHz to 40 MHz
T e 0 C to 70 C
CL e Circuit 1 and 2
RL e Circuit 1 and 2
Min Typ Max
Units
Notes
tRISE
Output Rise
tFALL
Output Fall
tSKEW
Maximum
Edge-to-Edge
Output Skew
CLK4
CLK2
CLK1
0 8V to 2 6V
1 0V to VCC b 1 0V
1 0V to VCC b 1 0V
CLK4
CLK2
CLK1
2 6V to 0 8V
VCC b 1 0V to 1 0V
VCC b 1 0V to 1 0V
a to a Edges
a to a Edges
a to a Edges
CLK1 CLK1
CLK1 CLK4
CLK2 CLK4
2 0 ns (Note 1)
2 0 ns (Note 1)
500
1000 ps (Note 2)
1500
tLOCK
tCYCLE
Time to Lock the Output to the XTALIN Input
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
100 ms
49 51
49 51 % (Note 3)
35 65
JLT Output Jitter (Long Term)
JCC
Output Jitter
CLK1
(Cycle to Cycle) CLK2
300 ps (Notes 4 5)
b75
a75 ps (Notes 4 5 6)
g250
ps (Notes 4 5 7)
CLK4
g250
ps (Notes 4 5 7)
FMIN
Minimum XTALIN Frequency
15 MHz
FMAX
Maximum XTALIN Frequency
43 MHz
Note 1 tRISE and tFALL parameters are measured at the pin of the device
Note 2 Skew is measured at 50% of VCC for CLK1 and CLK2 While it is measured at 1 4V for CLK4
Note 3 Output duty cycle is measured at VDD 2 for CLK1 and CLK2 While it is measured at 1 4V for CLK4
Note 4 Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles
It is also measured at output levels of VCC 2 Refer to Figure 2 for further explanation
Note 5 The GNDA pins of the 702 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB
Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin
Note 6 Cycle to Cycle Jitter is measured at VCC 2
Note 7 Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25 C 5V measured VCC 2
TL F 12386 – 4
Circuit 1 Test Circuit for CLK1 and CLK2
TL F 12386 – 5
Circuit 2 Test Circuit for CLK4
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CGS702V.PDF ] | |
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