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PDF 74LVC2G125-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G125-Q100 | |
| Descripción | Dual bus buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
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74LVC2G125-Q100
Dual bus buffer/line driver; 3-state
Rev. 1 — 8 May 2013
Product data sheet
1. General description
The 74LVC2G125-Q100 provides a dual non-inverting buffer/line driver with 3-state
output. The output enable input (pin nOE) controls the 3-state output. A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
1 page  
NXP Semiconductors
74LVC2G125-Q100
Dual bus buffer/line driver; 3-state
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Min
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V
0.65VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2.0
VCC = 4.5 V to 5.5 V
0.7VCC
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
-
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
-
-
VCC = 4.5 V to 5.5 V
-
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
-
IO = 4 mA; VCC = 1.65 V
-
IO = 8 mA; VCC = 2.3 V
-
IO = 12 mA; VCC = 2.7 V
-
IO = 24 mA; VCC = 3.0 V
-
IO = 32 mA; VCC = 4.5 V
-
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VCC 0.1
1.2
1.9
2.2
2.3
3.8
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
-
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
ICC
ICC
supply current
additional supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
per pin; VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
CI input capacitance
-
Typ[1] Max
Unit
--
V
--
V
--
V
--
V
- 0.35VCC V
- 0.7
V
- 0.8
V
- 0.3VCC V
- 0.1
V
- 0.45 V
- 0.3
V
- 0.4
V
- 0.55 V
- 0.55 V
--
--
--
--
--
--
0.1 5
0.1 10
0.1 10
0.1 10
5 500
2-
V
V
V
V
V
V
A
A
A
A
A
pF
74LVC2G125_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
74LVC2G125-Q100
Dual bus buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
y
Z
8
5
pin 1 index
E
c
HE
A A2
A1
1
e
4
bp w M
detail X
A
X
vM A
Q
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(2) e
HE
L
Lp
Q
v
w
y Z(1) θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40 0.21
0.15 0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
IEC
REFERENCES
JEDEC
JEITA
MO-187
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 8. Package outline SOT765-1 (VSSOP8)
74LVC2G125_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 May 2013
© NXP B.V. 2013. All rights reserved.
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