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PDF 74LVC2G126-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G126-Q100 | |
| Descripción | Bus buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
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74LVC2G126-Q100
Bus buffer/line driver; 3-state
Rev. 1 — 13 May 2015
Product data sheet
1. General description
The 74LVC2G126-Q100 is a dual non-inverting buffer/line driver with 3-state outputs. An
output enable input (pin nOE) controls each 3-state output. A LOW-level at pin nOE
causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all
inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G126-Q100 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
1 page  
NXP Semiconductors
74LVC2G126-Q100
Bus buffer/line driver; 3-state
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
IOFF power-off leakage current
ICC supply current
ICC additional supply current
CI input capacitance
Tamb = 40 C to +125 C
VIH HIGH-level input voltage
VIL LOW-level input voltage
VOL LOW-level output voltage
VOH HIGH-level output voltage
II
IOZ
IOFF
ICC
ICC
input leakage current
OFF-state output current
power-off leakage current
supply current
additional supply current
VI or VO = 5.5 V; VCC = 0 V
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
per pin; VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
VI or VO = 5.5 V; VCC = 0 V
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
per pin; VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
-
-
0.65 VCC
1.7
2.0
0.7 VCC
-
-
-
-
-
-
-
-
-
-
VCC 0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
Typ[1]
0.1
0.1
5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max Unit
10 A
10 A
500 A
- pF
-V
-V
-V
-V
0.35 VCC V
0.7 V
0.8 V
0.3 VCC V
0.1 V
0.70 V
0.45 V
0.60 V
0.80 V
0.80 V
-V
-V
-V
-V
-V
-V
20 A
20 A
20 A
40 A
5 mA
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVC2G126_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
74LVC2G126_Q100 v.1 20150512
Data sheet status
Product data sheet
74LVC2G126-Q100
Bus buffer/line driver; 3-state
Change notice
-
Supersedes
-
74LVC2G126_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 14
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