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74LVC2G86-Q100 PDF даташит

Спецификация 74LVC2G86-Q100 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Dual 2-input EXCLUSIVE-OR gate».

Детали детали

Номер произв 74LVC2G86-Q100
Описание Dual 2-input EXCLUSIVE-OR gate
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC2G86-Q100 Даташит, Описание, Даташиты
74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
Rev. 1 — 7 May 2013
Product data sheet
1. General description
The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options









No Preview Available !

74LVC2G86-Q100 Даташит, Описание, Даташиты
NXP Semiconductors
74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G86DP-Q100 40 C to +125 C TSSOP8
74LVC2G86DC-Q100 40 C to +125 C VSSOP8
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
4. Marking
Table 2. Marking codes
Type number
74LVC2G86DP-Q100
74LVC2G86DC-Q100
Marking code[1]
V86
V86
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A 1Y
1B
2A 2Y
2B
001aah760
Fig 1. Logic symbol
=1
=1
001aah761
Fig 2. IEC logic symbol
B
A
Fig 3. Logic diagram (one driver)
Y
mna040
74LVC2G86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 14









No Preview Available !

74LVC2G86-Q100 Даташит, Описание, Даташиты
NXP Semiconductors
74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
/9&*4
$ 
% 
< 
*1' 
Fig 4. Pin configuration SOT505-2 and SOT765-1
 9&&
 <
 %
 $
DDD
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
VCC
Pin description
Pin
1, 5
2, 6
4
7, 3
8
7. Functional description
Description
data input
data input
ground (0 V)
data output
supply voltage
Table 4.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level
Output
nY
L
H
H
L
74LVC2G86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 14










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