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PDF ADF4152HV Data sheet ( Hoja de datos )
| Número de pieza | ADF4152HV | |
| Descripción | Fractional-N/ Integer N PLL Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Voltage, Fractional-N/
Integer N PLL Synthesizer
ADF4152HV
FEATURES
GENERAL DESCRIPTION
Fractional-N synthesizer and integer N synthesizer
High voltage charge pump: VP = 6.0 V to 30 V
Radio frequency (RF) bandwidth to 5.0 GHz
Programmable output divider
Synthesizer power supply: 3.0 V to 3.6 V
Programmable dual-modulus prescaler
Programmable output power level
Programmable charge pump currents
RF output mute function
3-wire serial interface
Analog and digital lock detect
APPLICATIONS
Wireless infrastructure
Microwave point to point/point to multipoint radios
Very small aperture terminal (VSAT) radios
Test equipment
Private land mobile radios
The ADF4152HV is a 5.0 GHz, fractional-N or integer N
frequency synthesizer with an integrated high voltage charge
pump. The synthesizer can drive external wideband voltage
controlled oscillators (VCOs) directly, eliminating the need for
operational amplifiers to achieve higher tuning voltages. The
integrated high voltage charge pump simplifies design and
reduces cost while improving phase noise, in contrast to active
filter topologies, which tend to degrade phase noise compared
to passive filter topologies.
The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow
the user to generate RF output frequencies as low as 31.25 MHz.
For applications that require isolation, the RF output stage can be
muted. The mute function is both pin and software controllable.
A simple 3-wire interface controls all on-chip registers. The
charge pump operates from a power supply ranging from 6.0 V
to 30 V, whereas the rest of the device operates from 3.0 V to
3.6 V. The ADF4152HV can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDD
DVDD
VP
RSET
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
VALUE
VALUE
VALUE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
HIGH VOLTAGE
CHARGE
PUMP
PHASE
COMPARATOR
CURRENT
SETTING
÷1/÷2/
÷4/÷8/÷16
MULTIPLEXER
MUXOUT
LD
BOOST
MODE
OUTPUT
STAGE
RF
INPUT
CPOUT
RFOUT+
RFOUT–
PDBRF
RFIN+
RFIN–
CE
Figure 1.
GND
CPGND SDGND
ADF4152HV
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4152HV
Data Sheet
Parameter
POWER SUPPLIES
AVDD
DVDD, SDVDD
VP
IP
IDVDD + ISDVDD + IAVDD1
Current per Output Divider
IRFOUT2
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
Min Typ Max Unit Test Conditions/Comments
3.0 3.6 V
AVDD
V
6.0
30 V
Set the VP supply at least 1 V above the
maximum desired tuning voltage
1 2.5 mA VP = 30 V
50 60
mA
6 to 24
mA Each output divide by 2 consumes 6 mA
typical
20 32
mA RF output stage is programmable
1 µA
Output Frequency Using RF Output
Dividers
Second-Order Harmonic Distortion
31.25
Third-Order Harmonic Distortion
Minimum RF Output Power(RFOUT±)2
Maximum RF Output Power(RFOUT±)2
Output Power Variation vs. Supply
Output Power Variation vs. Temperature
Level of Signal with RF Mute Enabled
NOISE CHARACTERISTICS
Normalized In-Band Phase Noise Floor
(PNSYNTH)3
Normalized 1/f Phase Noise (PN1_f)4
RF Output Divider Noise Floor
Spurious Signals Due to Phase
Frequency Detector (PFD) Frequency
−19
−20
−13
−10
−4
5
±1
±1
−37
−213
−203
−113
−108
−155
−70
−85
MHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
500 MHz VCO input and divide by 16 selected
Fundamental VCO output
Divided VCO output
Fundamental VCO output
Divided VCO output
Programmable in 3 dB steps
Programmable in 3 dB steps
Pull-up supply on Pin 18 and Pin 19 varied
from 3.0 V to 3.6 V
From −40°C to +85°C
PDBRF pin brought low; RFOUT± = 2 GHz
Low noise mode
Low spur mode
Low noise mode
Low spur mode
Measured at 10 MHz offset
At RFOUT+/RFOUT− pins
At VCO output
1 TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 1.75 GHz.
2 Using 50 Ω resistors to AVDD, into a 50 Ω load.
3 This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
PNSYNTH = PNTOT − 10 log(fPFD) − 20 log N
where PNTOT is the measured in-band phase noise at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The flicker noise is specified at a 10 kHz offset and normalized to 1 GHz. The
formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both
the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
Rev. 0 | Page 4 of 27
5 Page 
ADF4152HV
–40
200kHz
600kHz
–50
400kHz
800kHz
–60
–70
–80
–90
–100
–110
–120
–130
1500
1505
1510
1515
1520
1525
FREQUENCY (MHz)
Figure 10. Fractional Spur Levels vs. Frequency, Low Noise Mode;
Measured at VCO Output, PFD = 25 MHz, MOD = 125
–40
25MHz
75MHz
50MHz
100MHz
–50
–60
–70
–80
–90
–100
–110
–120
1000
1200
1400
1600
1800
2000
FREQUENCY (MHz)
Figure 11. PFD and Reference Spur Levels vs. Frequency, Measured at VCO
Output, REFIN = 100 MHz, PFD = 25 MHz
–40
25MHz
75MHz
50MHz
100MHz
–50
–60
–70
–80
–90
–100
–110
–120
1000
1200
1400
1600
FREQUENCY (MHz)
1800
2000
Figure 12. PFD and Reference Spur Levels vs. Frequency, Measured at VCO
Output with ADL5541 Buffer Placed Between VCO Output and RF Input,
REFIN = 100 MHz, PFD = 25 MHz
Data Sheet
–80
–85
–90 LOW SPUR MODE
–95
–100
–105
LOW NOISE MODE
–110
1000
1050
1100
1150
1200
FREQUENCY (MHz)
1250
1300
Figure 13. In-Band Phase Noise Measured at 3 kHz Offset for Low Noise Mode
and Low Spur Mode, PFD = 25 MHz, PLL Loop Bandwidth = 40 kHz
4
2 +5dBm
0
+2dBm
–2
–4 –1dBm
–6
–4dBm
–8
–10
–12
–14
–16
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 14. Single-Ended RF Output Power Level vs. Frequency over Various
Power Settings, RF Output Pins Pulled Up to 3.3 V via 27 nH||50 Ω
Rev. 0 | Page 10 of 27
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADF4152HV.PDF ] | |
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