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GS81302T11GE PDF даташит

Спецификация GS81302T11GE изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «144Mb SigmaDDR-II+ Burst of 2 SRAM».

Детали детали

Номер произв GS81302T11GE
Описание 144Mb SigmaDDR-II+ Burst of 2 SRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS81302T11GE Даташит, Описание, Даташиты
GS81302T06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II+
Burst of 2 SRAM
500 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDRTM Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-IIFamily Overview
The GS81302T06/11/20/38E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302T06/11/20/38E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302T06/11/20/38E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.03c 11/2011
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology









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GS81302T11GE Даташит, Описание, Даташиты
GS81302T06/11/20/38E-500/450/400/350
4M x 36 SigmaDDR-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A CQ SA SA R/W BW2 K BW1 LD SA SA CQ
B
NC DQ27 DQ18 SA BW3
K
BW0
SA
NC
(288Mb)
NC
DQ8
C NC NC DQ28 VSS SA NC SA VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS VDDQ NC DQ15 DQ6
F
NC
DQ30 DQ21
VDDQ
VDD
VSS
VDD VDDQ NC
NC DQ5
G
NC
DQ31 DQ22
VDDQ
VDD
VSS
VDD VDDQ NC
NC DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD VDDQ NC DQ13 DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD VDDQ NC DQ12 DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ2
M
NC
NC DQ34 VSS VSS VSS VSS
VSS
NC
DQ11
DQ1
N
NC DQ35 DQ25 VSS
SA
SA
SA
VSS NC
NC DQ10
P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. Pin B9 is the expansion address.
Rev: 1.03c 11/2011
2/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology









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GS81302T11GE Даташит, Описание, Даташиты
GS81302T06/11/20/38E-500/450/400/350
8M x 18 SigmaDDR-II+ SRAM—Top View
123456789
A CQ SA SA R/W BW1 K SA LD SA
B
NC DQ9 NC
SA
NC
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA NC SA VSS NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC DQ15 NC
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N
NC
NC DQ16 VSS
SA
SA
SA
VSS NC
P NC NC DQ17 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. Pin B5 is the expansion address.
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Rev: 1.03c 11/2011
3/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology










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