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GS82583EQ36GK PDF даташит

Спецификация GS82583EQ36GK изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «288Mb SigmaQuad-IIIe Burst of 2 SRAM».

Детали детали

Номер произв GS82583EQ36GK
Описание 288Mb SigmaQuad-IIIe Burst of 2 SRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS82583EQ36GK Даташит, Описание, Даташиты
GS82583EQ18/36GK-500/450/400
260-Pin BGA
Commercial Temp
Industrial Temp
288Mb SigmaQuad-IIIe™
Burst of 2 SRAM
Up to 500 MHz
1.3V VDD
1.2V, 1.3V, or 1.5V VDDQ
Features
• 8Mb x 36 and 16Mb x 18 organizations available
• 500 MHz maximum operating frequency
• 1.0 BT/s peak transaction rate (in billions per second)
• 72 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• 1.3V nominal core voltage
• 1.2V, 1.3V, or 1.5V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIeFamily Overview
SigmaQuad-IIIe SRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Clocking and Addressing Schemes
The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B2
SRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 SRAM is always one address pin
less than the advertised index depth (e.g. the 16M x 18 has 8M
addressable index).
Speed Grade
-500
-450
-400
Parameter Synopsis
Max Operating Frequency
500 MHz
450 MHz
400 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.05 8/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology









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GS82583EQ36GK Даташит, Описание, Даташиты
GS82583EQ18/36GK-500/450/400
16M x 18 Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCH
(CFG)
MCL
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS NUO VSS
NUI
MVQ
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q17 VDDQ D17 VDDQ VSS SA VDD SA VSS VDDQ NUI VDDQ NUO
D
VSS NUO VSS
NUI
SA VDDQ SA VDDQ SA
D1
VSS
Q1
VSS
E Q16 VDDQ D16 VDD VSS SA VSS SA VSS VDD NUI VDDQ NUO
F VSS NUO VSS NUI SA VDD VDDQ VDD SA D2 VSS Q2 VSS
G Q15 NUO D15 NUI VSS SA MZT1 SA VSS D3 NUI Q3 NUO
H Q14 VDDQ D14 VDDQ SA VDDQ W VDDQ SA VDDQ NUI VDDQ NUO
J VSS NUO VSS NUI VSS SA VSS SA VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 Vss KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q13 VSS D13 VSS SA VSS SA VSS NUI VSS NUO VSS
N NUO VDDQ NUI VDDQ DLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5
P NUO Q12 NUI D12 VSS SA MZT0 SA VSS NUI D6 NUO Q6
R VSS Q11 VSS D11 MCH VDD VDDQ VDD RST NUI VSS NUO VSS
T NUO VDDQ NUI VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7
U
VSS
Q10
VSS
D10
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
NUI
VSS NUO
VSS
V
NUO VDDQ NUI VDDQ VSS
SA
(x18)
VDD
SA
(B2)
VSS VDDQ D8 VDDQ Q8
W
VSS
Q9
VSS
D9
TCK
MCL
NC
(RSVD)
MCL
TMS
NUI
VSS
NUO
VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ VDD VDDQ VDD
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.05 8/2016
2/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology









No Preview Available !

GS82583EQ36GK Даташит, Описание, Даташиты
GS82583EQ18/36GK-500/450/400
8M x 36 Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCL
(CFG)
MCL
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS
Q35
VSS
D35
MVQ
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q26 VDDQ D26 VDDQ VSS SA VDD SA VSS VDDQ D9 VDDQ Q9
D VSS Q34 VSS D34 SA VDDQ SA VDDQ SA D1 VSS Q1 VSS
E Q25 VDDQ D25 VDD VSS SA VSS SA VSS VDD D10 VDDQ Q10
F VSS Q33 VSS D33 SA VDD VDDQ VDD SA D2 VSS Q2 VSS
G Q24 Q32 D24 D32 VSS SA MZT1 SA VSS D3 D11 Q3 Q11
H Q23 VDDQ D23 VDDQ SA VDDQ W VDDQ SA VDDQ D12 VDDQ Q12
J VSS Q31 VSS D31 VSS SA VSS SA VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q22 VSS D22 VSS SA VSS SA VSS D13 VSS Q13 VSS
N Q30 VDDQ D30 VDDQ DLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5
P Q29 Q21 D29 D21 VSS SA MZT0 SA VSS D14 D6 Q14 Q6
R VSS Q20 VSS D20 MCH VDD VDDQ VDD RST D15 VSS Q15 VSS
T Q28 VDDQ D28 VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7
U
VSS
Q19
VSS
D19
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
D16
VSS
Q16
VSS
V
Q27 VDDQ D27 VDDQ VSS
NUI
(x18)
VDD
SA
(B2)
VSS VDDQ D8 VDDQ Q8
W
VSS
Q18
VSS
D18
TCK
MCL
NC
(RSVD)
MCL
TMS
D17
VSS
Q17
VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ VDD VDDQ VDD
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.05 8/2016
3/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology










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