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GS8182S09BD PDF даташит

Спецификация GS8182S09BD изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «18Mb Burst of 2 SigmaSIO DDR-II SRAM».

Детали детали

Номер произв GS8182S09BD
Описание 18Mb Burst of 2 SigmaSIO DDR-II SRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS8182S09BD Даташит, Описание, Даташиты
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaSIO DDR-IITM SRAM
400 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaSIO DDR-IIFamily Overview
GS8182S08/09/18/36BD are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 2M x 8 has a 1M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.03c 11/2011
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology









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GS8182S09BD Даташит, Описание, Даташиты
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
2M x 8 SigmaQuad SRAM—Top View
123456789
A
CQ
NC/SA
(72Mb)
SA
R/W NW1
K
NC/SA
(144Mb)
LD
SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
NW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D4 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D5
Q5
VDDQ
VDD
VSS
VDD VDDQ NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D7 NC VSS SA SA SA VSS NC
P NC NC Q7 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Note:
NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
10
NC/SA
(36Mb)
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
Rev: 1.03c 11/2011
2/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology









No Preview Available !

GS8182S09BD Даташит, Описание, Даташиты
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
12
A
CQ
NC/SA
(72Mb)
B NC NC
C NC NC
D NC D5
E NC NC
F NC NC
G NC D6
H Doff VREF
J NC NC
K NC NC
L NC Q7
M NC NC
N NC D8
P NC NC
R TDO TCK
Note:
BW controls writes to D0:D7.
2M x 9 SigmaQuad SRAM—Top View
3
SA
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
45678
R/W NC
K
NC/SA
(144Mb)
LD
SA
NC/SA
(288Mb)
K
BW SA
VSS SA SA SA VSS
VSS VSS VSS VSS VSS
VDDQ
VSS
VSS
VSS VDDQ
VDDQ
VDD
VSS
VDD VDDQ
VDDQ
VDD
VSS
VDD VDDQ
VDDQ
VDD
VSS
VDD VDDQ
VDDQ
VDD
VSS
VDD VDDQ
VDDQ
VDD
VSS
VDD VDDQ
VDDQ
VSS
VSS
VSS VDDQ
VSS VSS VSS VSS VSS
VSS SA SA SA VSS
SA SA C SA SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA SA SA C SA SA SA
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
10
NC/SA
(36Mb)
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Rev: 1.03c 11/2011
3/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology










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