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GS8182S18D PDF даташит

Спецификация GS8182S18D изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «18Mb Burst of 2 DDR SigmaSIO-II SRAM».

Детали детали

Номер произв GS8182S18D
Описание 18Mb Burst of 2 DDR SigmaSIO-II SRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS8182S18D Даташит, Описание, Даташиты
GS8182S18D-267/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
DDR SigmaSIO-II SRAM
267 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
SigmaRAMFamily Overview
GS8182S18 are built in compliance with the SigmaSIO-II
SRAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage HSTL I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-267
3.75 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.08a 8/2005
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology









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GS8182S18D Даташит, Описание, Даташиты
GS8182S18D-267/250/200/167
1M x 18 SigmaQuad SRAM—Top View
123456789
A
CQ
VSS/SA NC/SA
(144Mb) (36Mb)
R/W
BW1
K
NC LD SA
B NC Q9 D9 SA NC K BW0 SA NC
C NC NC D10 VSS SA SA SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. It is recommended that H1 be tied low for compatibility with future devices.
10
VSS/SA
(72Mb)
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.08a 8/2005
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology









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GS8182S18D Даташит, Описание, Даташиты
GS8182S18D-267/250/200/167
Pin Description Table
Symbol
Description
Type Comments
SA Synchronous Address Inputs Input —
NC
No Connect
——
R/W
Synchronous Read/Write
Input
BW0–BW1
Synchronous Byte Writes
Input Active Low
K
Input Clock
Input Active High
C
Output Clock
Input Active High
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input
ZQ
Output Impedance Matching Input
Input
K
Input Clock
Input Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
— Active Low
LD
Synchronous Load Pin
— Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
D
Synchronous Data Inputs
Input
Q
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left uncon-
nected.
3. NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Rev: 1.08a 8/2005
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology










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