74HC30-Q100 PDF даташит
Спецификация 74HC30-Q100 изготовлена «NXP Semiconductors» и имеет функцию, называемую «8-input NAND gate». |
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Детали детали
Номер произв | 74HC30-Q100 |
Описание | 8-input NAND gate |
Производители | NXP Semiconductors |
логотип |
14 Pages
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74HC30-Q100; 74HCT30-Q100
8-input NAND gate
Rev. 1 — 30 January 2013
Product data sheet
1. General description
The 74HC30-Q100; 74HCT30-Q100 is an 8-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC30-Q100: CMOS level
For 74HCT30-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC30D-Q100 40 C to +125 C SO14
74HCT30D-Q100
74HC30PW-Q100 40 C to +125 C TSSOP14
74HCT30PW-Q100
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
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NXP Semiconductors
4. Functional diagram
1A
2B
3C
4D
5E
6F
11 G
12 H
Fig 1. Logic symbol
Y8
mna488
Fig 3. Logic diagram
A
B
C
D
E
F
G
H
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
1&
2
3
4
5
6
11
12
8
mna489
Fig 2. IEC logic symbol
Y
mna490
74HC_HCT30_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 January 2013
© NXP B.V. 2013. All rights reserved.
2 of 14
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NXP Semiconductors
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
5. Pinning information
5.1 Pinning
$
%
&
'
(
)
*1'
Fig 4. Pin configuration SO14 and TSSOP14
+&4
+&74
9&&
QF
+
*
QF
QF
<
DDD
5.2 Pin description
Table 2.
Symbol
A
B
C
D
E
F
GND
Y
n.c.
n.c.
G
H
n.c.
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
not connected
data input
data input
not connected
supply voltage
74HC_HCT30_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 January 2013
© NXP B.V. 2013. All rights reserved.
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74HC30-Q100 | 8-input NAND gate | NXP Semiconductors |
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