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PDF 74HC40103 Data sheet ( Hoja de datos )
| Número de pieza | 74HC40103 | |
| Descripción | 8-bit synchronous binary down counter | |
| Fabricantes | NXP Semiconductors | |
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74HC40103
8-bit synchronous binary down counter
Rev. 5 — 21 April 2016
Product data sheet
1. General description
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling
or disabling the clock (CP), for clearing the counter to its maximum count and for
presetting the counter either synchronously or asynchronously. In normal operation, the
counter is decremented by one count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count
output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for
one full clock period. When the synchronous preset enable input (PE) is LOW, data at the
jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition
regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW,
data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of
the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its
maximum count (decimal 255) regardless of the state of any other input. If all control
inputs except TE are HIGH at the time of zero count, the counters will jump to the
maximum count, giving a counting sequence of 256 clock pulses long. Device may be
cascaded using the TE input and the TC output, in either a synchronous or ripple mode.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
2. Features and benefits
Cascadable
Synchronous or asynchronous preset
Low-power dissipation
Complies with JEDEC standard no. 7A
CMOS input levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C
3. Applications
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters.
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
74HC40103
8-bit synchronous binary down counter
Fig 6. Pin configuration
&3
05
7(
3
3
3
3
*1'
9&&
3(
7&
3
3
3
3
3/
DDE
6.2 Pin description
Table 2.
Symbol
CP
MR
TE
P0
P1
P2
P3
GND
PL
P4
P5
P5
P7
TC
PE
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input (active LOW)
jam input 0
jam input 1
jam input 2
jam input 3
ground (0 V)
asynchronous preset enable input (active LOW)
jam input 4
jam input 5
jam input 6
jam input 7
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
74HC40103
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
74HC40103
8-bit synchronous binary down counter
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 13.
Symbol Parameter
Conditions
fmax maximum frequency see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
CPD power dissipation
capacitance
VI = GND to VCC
Tamb = 40 C to +85 C
tpd propagation delay
CP to TC; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
TE to TC; see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
PL to TC; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tPHL HIGH to LOW
MR to TC; see Figure 9
propagation delay
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tt transition time
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tW pulse width
CP HIGH or LOW; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
MR LOW; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
PL LOW; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min Typ Max Unit
3.0
15
18
-
[3] -
10
29
35
32
24
- MHz
- MHz
- MHz
- MHz
- pF
[1]
-
-
-
- 375 ns
- 75 ns
- 64 ns
- - 220 ns
- - 44 ns
- - 37 ns
- - 395 ns
- - 79 ns
- - 40 ns
-
-
-
[2]
-
-
-
- 345 ns
- 69 ns
- 59 ns
- 95 ns
- 19 ns
- 16 ns
205 -
41 -
35 -
- ns
- ns
- ns
155 -
31 -
26 -
- ns
- ns
- ns
155 -
31 -
26 -
- ns
- ns
- ns
74HC40103
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 23
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