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74AUP1G58 PDF даташит

Спецификация 74AUP1G58 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Low-power configurable multiple function gate».

Детали детали

Номер произв 74AUP1G58
Описание Low-power configurable multiple function gate
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74AUP1G58 Даташит, Описание, Даташиты
74AUP1G58
Low-power configurable multiple function gate
Rev. 7 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G58 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VTis defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C









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74AUP1G58 Даташит, Описание, Даташиты
NXP Semiconductors
74AUP1G58
Low-power configurable multiple function gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G58GW 40 C to +125 C SC-88
74AUP1G58GM 40 C to +125 C XSON6
74AUP1G58GF 40 C to +125 C XSON6
74AUP1G58GN 40 C to +125 C XSON6
74AUP1G58GS 40 C to +125 C XSON6
74AUP1G58GX 40 C to +125 C X2SON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
plastic thermal extremely thin small outline package; SOT1255
no leads; 6 terminals; body 1 0.8 0.35 mm
4. Marking
Table 2. Marking
Type number
74AUP1G58GW
74AUP1G58GM
74AUP1G58GF
74AUP1G58GN
74AUP1G58GS
74AUP1G58GX
Marking code[1]
aK
aK
aK
aK
aK
aK
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1. Logic symbol
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74AUP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 24









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74AUP1G58 Даташит, Описание, Даташиты
NXP Semiconductors
6. Pinning information
6.1 Pinning
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 9&&
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Fig 2. Pin configuration SOT363
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 9&&
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DDG
7UDQVSDUHQWWRSYLHZ
Fig 4. Pin configuration SOT891, SOT1115 and
SOT1202
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
VCC
C
Pin description
Pin
1
2
3
4
5
6
74AUP1G58
Low-power configurable multiple function gate
$83*
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*1' 
 9&&
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DDG
7UDQVSDUHQWWRSYLHZ
Fig 3. Pin configuration SOT886
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*1'

9&&

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DDD
7UDQVSDUHQWWRSYLHZ
Fig 5. Pin configuration SOT1255 (X2SON6)
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
74AUP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 24










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