74LVC2G38 PDF даташит
Спецификация 74LVC2G38 изготовлена «Philips» и имеет функцию, называемую «Dual 2-input NAND gate». |
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Детали детали
Номер произв | 74LVC2G38 |
Описание | Dual 2-input NAND gate |
Производители | Philips |
логотип |
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INTEGRATED CIRCUITS
DATA SHEET
74LVC2G38
Dual 2-input NAND gate
(open drain)
Product specification
Supersedes data of 2003 Oct 27
2004 Oct 18
No Preview Available ! |
Philips Semiconductors
Dual 2-input NAND gate (open drain)
Product specification
74LVC2G38
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Open drain outputs
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC2G38 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G38 provides the 2-input NAND function.
The outputs of the 74LVC2G38 devices are open drain
and can be connected to other open-drain outputs to
implement active-LOW, wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPZL/tPLZ
PARAMETER
propagation delay inputs nA and nB to
output nY
CI input capacitance
CPD power dissipation capacitance per gate
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.0 ns
1.8 ns
2.5 ns
2.1 ns
1.5 ns
2.5 pF
5 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
2004 Oct 18
2
No Preview Available ! |
Philips Semiconductors
Dual 2-input NAND gate (open drain)
Product specification
74LVC2G38
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
nB
L
H
L
H
OUTPUT
nY
Z
Z
Z
L
ORDERING INFORMATION
TYPE NUMBER
74LVC2G38DP
74LVC2G38DC
74LVC2G38GM
TEMPERATURE RANGE
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
PINS
8
8
8
PACKAGE
PACKAGE
TSSOP8
VSSOP8
XSON8
MATERIAL
plastic
plastic
plastic
CODE
SOT505-2
SOT765-1
SOT833-1
MARKING
Y38
Y38
Y38
PINNING
PIN
1
2
3
4
5
6
7
8
1A
1B
2Y
GND
2A
2B
1Y
VCC
SYMBOL
data input
data input
data output
ground (0 V)
data input
data input
data output
supply voltage
DESCRIPTION
2004 Oct 18
3
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