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PDF 74LVC573A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC573A | |
| Descripción | OCTAL D-TYPE LATCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74LVC573A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
)|IOH| = IOL = 24mA (MIN) at VCC = 3V
t(ss PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
cs BALANCED PROPAGATION DELAYS:
utPLH ≅ tPHL
ds OPERATING VOLTAGE RANGE:
roVCC(OPR) = 1.65V to 3.6V (1.2V Data
PRetention)
s PIN AND FUNCTION COMPATIBLE WITH
te74 SERIES 573
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC573AMTR
74LVC573ATTR
les LATCH-UP PERFORMANCE EXCEEDS
o500mA (JESD 17)
outputs will follow the data input precisely or
bss ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
OMM > 200V
t(s) -DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
cD-TYPE LATCH fabricated with sub-micron silicon
dugate and double-layer metal wiring C2MOS
rotechnology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
Papplications.
teThese 8 bit D-Type latch are controlled by a latch
leenable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
ObsoFigure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 3
1/13
1 page  
74LVC573A
Table 9: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
(note 1)
VCC
(V)
1.8
2.5
3.3
fIN = 10MHz
TA = 25 °C
Min. Typ. Max.
4
28
30
34
Unit
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
)Figure 3: Test Circuit
duct(s) - Obsolete Product(sRT = ZOUT of pulse generator (typically 50Ω)
roTable 10: Test Circuit And Waveform Symbol Value
te PSymbol
oleCL
bsRL = R1
O VS
1.65 to 1.95V
30pF
1000Ω
2 x VCC
2.3 to 2.7V
30pF
500Ω
2 x VCC
VCC
2.7V
50pF
500Ω
6V
3.0 to 3.6V
50pF
500Ω
7V
VIH VCC VCC 2.7V 3.0V
VM
VCC/2
VCC/2
1.5V
1.5V
VOH
VCC
VCC
3.0V
3.5V
VX
VOL + 0.15V
VOL + 0.15V
VOL + 0.3V
VOL + 0.3V
VY
VOH - 0.15V
VOH - 0.15V
VOH - 0.3V
VOH - 0.3V
tr = tr
<2.0ns
<2.0ns
<2.5ns
<2.5ns
5/13
5 Page 
74LVC573A
Tape & Reel TSSOP20 MECHANICAL DATA
DIM.
MIN.
mm.
TYP
MAX.
MIN.
inch
TYP.
MAX.
A 330 12.992
C 12.8
13.2 0.504
0.519
D 20.2
0.795
N 60
t(s)T
cAo 6.8
duBo 6.9
roKo 1.7
PPo 3.9
Obsolete Product(s) - ObsoleteP 11.9
2.362
22.4
7 0.268
7.1 0.272
1.9 0.067
4.1 0.153
12.1 0.468
0.882
0.276
0.280
0.075
0.161
0.476
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74LVC573A.PDF ] | |
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