PDF CD82C59A Data sheet ( Hoja de datos )

Número de pieza	CD82C59A
Descripción	CMOS Priority Interrupt Controller
Fabricantes	Intersil Corporation
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No Preview Available ! 82C59A March 1997 CMOS Priority Interrupt Controller Features Description • 12.5MHz, 8MHz and 5MHz Versions Available - 12.5MHz Operation . . . . . . . . . . . . . . . . . . . 82C59A-12 - 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A - 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5 • High Speed, “No Wait-State” Operation with 12.5MHz 80C286 and 8MHz 80C86/88 • Pin Compatible with NMOS 8259A • 80C86/88/286 and 8080/85/86/88/286 Compatible • Eight-Level Priority Controller, Expandable to 64 Levels • Programmable Interrupt Modes • Individual Request Mask Capability • Fully Static Design • Fully TTL Compatible • Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum - ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum The Intersil 82C59A is a high performance CMOS Priority Interrupt Controller manufactured using an advanced 2µm CMOS process. The 82C59A is designed to relieve the sys- tem CPU from the task of polling in a multilevel priority system. The high speed and industry standard conﬁguration of the 82C59A make it compatible with micro- processors such as 80C286, 80286, 80C86/88, 8086/88, 8080/85 and NSC800. The 82C59A can handle up to eight vectored priority inter- rupting sources and is cascadable to 64 without additional circuitry. Individual interrupting sources can be masked or prioritized to allow custom system conﬁguration. Two modes of operation make the 82C59A compatible with both 8080/85 and 80C86/88/286 formats. Static CMOS circuit design ensures low operating power. The Intersil advanced CMOS process results in performance equal to or greater than existing equivalent products at a fraction of the power. • Single 5V Power Supply • Operating Temperature Ranges - C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC - I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C59A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Ordering Information 5MHz CP82C59A-5 IP82C59A-5 CS82C59A-5 IS82C59A-5 CD82C59A-5 ID82C59A-5 MD82C59A-5/B 5962-8501601YA MR82C59A-5/B 5962-85016013A CM82C59A-5 PART NUMBER 8MHz CP82C59A IP82C59A CS82C59A IS82C59A CD82C59A ID82C59A MD82C59A/B 5962-8501602YA MR82C59A/B 5962-85016023A CM82C59A 12.5MHz CP82C59A-12 IP82C59A-12 CS82C59A-12 IS82C59A-12 CD82C59A-12 ID82C59A-12 MD82C59A-12/B - MR82C59A-12/B - CM82C59A-12 PACKAGE 28 Ld PDIP 28 Ld PLCC CERDIP SMD# 28 Pad CLCC SMD# 28 Ld SOIC TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC -55oC to +125oC 0oC to +70oC PKG. NO. E28.6 E28.6 N28.45 N28.45 F28.6 F28.6 F28.6 F28.6 J28.A J28.A M28.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 4-1 File Number 2784.2 1 page 82C59A Priority Resolver This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the cor- responding bit of the lSR during the INTA sequence. Interrupt Mask Register (IMR) The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority. Interrupt (INT) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286 input levels. Interrupt Acknowledge (INTA) INTA pulses will cause the 82C59A to release vectoring information onto the data bus. The format of this data depends on the system mode (µPM) of the 82C59A. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer. Read/Write Control Logic The function of this block is to accept output commands from the CPU. It contains the Initialization Command Word (lCW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 82C59A to be transferred onto the Data Bus. Chip Select (CS) A LOW on this input enables the 82C59A. No reading or writing of the device will occur unless the device is selected. Write (WR) A LOW on this input enables the CPU to write control words (lCWs and OCWs) to the 82C59A. Read (RD) A LOW on this input enables the 82C59A to send the status of the Interrupt Request Register (lRR), In-Service Register (lSR), the Interrupt Mask Register (lMR), or the interrupt level (in the poll mode) onto the Data Bus. A0 This input signal is used in conjunction with WR and RD sig- nals to write commands into the various command registers, as well as to read the various status registers of the chip. This line can be tied directly to one of the system address lines. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 82C59As used in the system. The associated three I/O pins (CAS0 - 2) are outputs when the 82C59A is used as a mas- ter and are inputs when the 82C59A is used as a slave. As a master, the 82C59A sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section “Cascading the 82C59A”.) Interrupt Sequence The powerful features of the 82C59A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the speciﬁed interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. These events occur in an 8080/8085 system: 1. One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are raised high, setting the corresponding IRR bit(s). 2. The 82C59A evaluates those requests in the priority resolver and sends an interrupt (INT) to the CPU, if appropriate. 3. The CPU acknowledges the lNT and responds with an INTA pulse. 4. Upon receiving an lNTA from the CPU group, the highest priority lSR bit is set, and the corresponding lRR bit is reset. The 82C59A will also release a CALL instruction code (11001101) onto the 8-bit data bus through D0 - D7. 5. This CALL instruction will initiate two additional INTA pulses to be sent to 82C59A from the CPU group. 6. These two INTA pulses allow the 82C59A to release its preprogrammed subroutine address onto the data bus. The lower 8-bit address is released at the ﬁrst INTA pulse and the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction released by the 82C59A. In the AEOI mode, the lSR bit is reset at the end of the third INTA pulse. Otherwise, the lSR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence. The events occurring in an 80C86/88/286 system are the same until step 4. 4. The 82C59A does not drive the data bus during the ﬁrst INTA pulse. 5. The 80C86/88/286 CPU will initiate a second INTA pulse. During this INTA pulse, the appropriate ISR bit is set and the corresponding bit in the IRR is reset. The 82C59A outputs the 8-bit pointer onto the data bus to be read by the CPU. 4-5 5 Page 82C59A End of Interrupt (EOI) The In-Service (IS) bit can be reset either automatically fol- lowing the trailing edge of the last in sequence INTA pulse (when AEOI bit in lCW1 is set) or by a command word that must be issued to the 82C59A before returning from a ser- vice routine (EOI Command). An EOI command must be issued twice if servicing a slave in the Cascade mode, once for the master and once for the corresponding slave. There are two forms of EOl command: Speciﬁc and Non- Speciﬁc. When the 82C59A is operated in modes which pre- serve the fully nested structure, it can determine which IS bit to reset on EOI. When a Non-Speciﬁc command is issued the 82C59A will automatically reset the highest IS bit of those that are set, since in the fully nested mode the highest IS level was necessarily the last level acknowledged and serviced. A non-speciﬁc EOI can be issued with OCW2 (EOl = 1, SL = 0, R = 0). When a mode is used which may disturb the fully nested structure, the 82C59A may no longer be able to determine the last level acknowledged. In this case a Speciﬁc End of Interrupt must be issued which includes as part of the com- mand the IS level to be reset. A speciﬁc EOl can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the binary level of the IS bit to be reset). An lRR bit that is masked by an lMR bit will not be cleared by a non-speciﬁc EOI if the 82C59A is in the Special Mask Mode. Automatic End of Interrupt (AEOI) Mode If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl mode continuously until reprogrammed by lCW4. In this mode the 82C59A will automatically perform a non-speciﬁc EOI operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in 8080/85, second in 80C86/88/286). Note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single 82C59A. Automatic Rotation (Equal Priority Devices) In some applications there are a number of interrupting devices of equal priority. In this mode a device, after being serviced, receives the lowest priority, so a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once. For example, if the priority and “in service” status is: Before Rotate (lR4 the highest priority requiring service) IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 “IS” Status 0 1 0 1 0 0 0 0 Priority Status 76543210 lowest highest After Rotate (lR4 was serviced, all other priorities rotated correspondingly) IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 “IS” Status 0 1 0 0 0 0 0 0 Priority Status 21076543 highest lowest There are two ways to accomplish Automatic Rotation using OCW2, the Rotation on Non-Speciﬁc EOI Command (R = 1, SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared by (R = 0, SL = 0, EOl = 0). Speciﬁc Rotation (Speciﬁc Priority) The programmer can change priorities by programming the lowest priority and thus, ﬁxing all other priorities; i.e., if IR5 is programmed as the lowest priority device, then IR6 will have the highest one. The Set Priority command is issued in OCW2 where: R = 1, SL = 1, L0 - L2 is the binary priority level code of the lowest priority device. Observe that in this mode internal status is updated by soft- ware control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command by using the Rotate on Speciﬁc EOl command in OCW2 (R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive low- est priority). Interrupt Masks Each Interrupt Request input can be masked individually by the Interrupt Mask Register (IMR) programmed through OCW1. Each bit in the lMR masks one interrupt channel if it is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth. Masking an IR channel does not affect the operation of other channels. Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The difﬁculty here is that if an Interrupt Request is acknowl- edged and an End of Interrupt command did not reset its IS bit (i.e., while executing a service routine), the 82C59A would have inhibited all lower priority requests with no easy way for the routine to enable them. That is where the Special Mask Mode comes in. In the Spe- cial Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading the mask register. 4-11 11 Page

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