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CD82C86H PDF даташит

Спецификация CD82C86H изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Octal Bus Transceiver».

Детали детали

Номер произв CD82C86H
Описание CMOS Octal Bus Transceiver
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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CD82C86H Даташит, Описание, Даташиты
82C86H
March 1997
CMOS Octal Bus Transceiver
Features
Description
• Full Eight Bit Bi-Directional Bus Interface
• Industry Standard 8286 Compatible Pinout
• High Drive Capability
- B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
- A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
• Three-State Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C86H provides a full
eight-bit bi-directional bus interface in a 20 lead package. The
Transmit (T) control determines the data direction. The active
low output enable (OE) permits simple interface to the 80C86,
80C88 and other microprocessors. The 82C86H has gated
inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Range
- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- I82C86H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C86H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NUMBER
5MHz
8MHz
PACK-
AGE
CP82C86H-5 CP82C86H 20 Ld
PDIP
IP82C86H-5 IP82C86H
CS82C86H-5 CS82C86H 20 Ld
PLCC
IS82C86H-5 IS82C86H
CD82C86H-5 CD82C86H 20 Ld
CERDIP
ID82C86H-5 ID82C86H
MD82C86H-5/B
-
PKG.
TEMP. RANGE NO.
0oC to +70oC E20.3
-40oC to +85oC E20.3
0oC to +70oC N20.35
-40oC to +85oC N20.35
0oC to +70oC F20.3
-40oC to +85oC F20.3
-55oC to
+125oC
F20.3
5962-
8757701RA
- SMD #
F20.3
MR82C86H-5/B - 20 Pad
CLCC
-55oC to
+125oC
J20.A
5962-
87577012A
- SMD #
J20.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-317
File Number 2977.1









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CD82C86H Даташит, Описание, Даташиты
Pinouts
82C86H (PDIP, CERDIP)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
OE 9
GND 10
20 VCC
19 B0
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 T
82C86H
82C86H (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
A3 4
A4 5
A5 6
A6 7
A7 8
18 B1
17 B2
16 B3
15 B4
14 B5
9 10 11 12 13
TRUTH TABLE
T OE A
X H Hi-Z
HL
I
L LO
H = Logic One
L = Logic Zero
I = Input Mode
O = Output Mode
X = Don’t Care
Hi-Z = High Impedance
B
Hi-Z
O
I
PIN
A0-A7
B0-B7
T
OE
PIN NAMES
DESCRIPTION
Local Bus Data I/O Pins
System Bus Data I/O Pins
Transmit Control Input
Active Low Output Enable
4-318









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CD82C86H Даташит, Описание, Даташиты
82C86H
Functional Diagram
Decoupling Capacitors
The transient current required to charge and discharge the
A0 300pF load capacitance specified in the 82C86H/87H data
B0 sheet is determined by:
A1 B1 I = CL(dv dt)
(EQ. 1)
A2 B2
Assuming that all outputs change state at the same time and
A3 B3 that dv/dt is constant;
A4
A5
B4
B5
I = CL(--V-----C----t-C-R-----×----t-8-F--0----%------)
(EQ. 2)
A6 B6 where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
A7 B7
I = (80 × 300 × 1012) × (5.0V × 0.8) ⁄ (20 × 109)
(EQ. 3)
= 480mA
OE
T
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the VCC and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from VCC to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
STB
DATA IN
VCC
VCC
P
P
N
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
VCC
OE
DATA IN
P
P
INTERNAL
DATA
VCC
N
P
N
N
FIGURE 2. 82C86H/87H GATED INPUTS
This current spike may cause a large negative voltage spike
on VCC which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1µF
ceramic disc capacitor be placed between VCC and GND at
each device, with placement being as near to the device as
possible.
4-319










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Номер в каталогеОписаниеПроизводители
CD82C86HCMOS Octal Bus TransceiverIntersil Corporation
Intersil Corporation
CD82C86H-5CMOS Octal Bus TransceiverIntersil Corporation
Intersil Corporation

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