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S25FL064P PDF даташит

Спецификация S25FL064P изготовлена ​​​​«Cypress» и имеет функцию, называемую «64-Mbit 3.0 V SPI Flash Memory».

Детали детали

Номер произв S25FL064P
Описание 64-Mbit 3.0 V SPI Flash Memory
Производители Cypress
логотип Cypress логотип 

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S25FL064P Даташит, Описание, Даташиты
S25FL064P
64-Mbit 3.0 V SPI Flash Memory
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64-kB sectors
– Top or bottom parameter block (Two 64-kB sectors (top
or bottom) broken down into sixteen 4-kB sub-sectors
each)
– 256-byte page size
– Backward compatible with the S25FL064A device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64-kB sectors
– Sub-sector erase (P4E) command (20h) for 4-kB sectors
– Sub-sector erase (P8E) command (40h) for 8-kB sectors
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory
or by the customer
CFI (Common Flash Interface) compliant: allows host system
to identify and accommodate multiple flash devices
Process technology
– Manufactured on 90-nm MirrorBit® process technology
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 8 mm)
– 24-ball BGA package (6 8 mm), 5 5 pin configuration
– 24-ball BGA package (6 8 mm), 6 4 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 A (typical)
– Deep Power-Down Mode 3 A (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits
to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Software Features
– SPI Bus Compatible Serial Interface
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00649 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 18, 2016









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S25FL064P Даташит, Описание, Даташиты
S25FL064P
General Description
The S25FL064P is a 3.0 Volt (2.7V to 3.6V), single-power-supply flash memory device. The device consists of 128 uniform 64 kB
sectors with the two (Top or Bottom) 64 kB sectors further split up into thirty-two 4 kB sub sectors. The S25FL064P device is fully
backward compatible with the S25FL064A device.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be
programmed in-system with the standard system 3.0-volt VCC supply.
The S25FL064P device adds the following high-performance features using 5 new instructions:
Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz
Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz
Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz
Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a clock rate of up to 80
MHz
Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase
and Bulk Erase commands.
Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and
regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable
the Accelerated Programming mode.
The S25FL064P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for permanent secure
identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or
OTPR instructions.
Document Number: 002-00649 Rev. *I
Page 2 of 62









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S25FL064P Даташит, Описание, Даташиты
S25FL064P
Contents
1. Block Diagram.............................................................. 4
2. Connection Diagrams.................................................. 5
3. Input/Output Descriptions........................................... 7
4. Logic Symbol ............................................................... 7
5. Ordering Information ................................................... 8
5.1 Valid Combinations ........................................................ 9
6. SPI Modes................................................................... 10
7. Device Operations ..................................................... 11
7.1 Byte or Page Programming.......................................... 11
7.2 Quad Page Programming ............................................ 11
7.3 Dual and Quad I/O Mode ............................................. 11
7.4 Sector Erase / Bulk Erase............................................ 11
7.5 Monitoring Write Operations
Using the Status Register ............................................ 11
7.6 Active Power and Standby Power Modes.................... 11
7.7 Status Register ............................................................ 12
7.8 Configuration Register ................................................. 12
7.9 Data Protection Modes ................................................ 13
7.10 Hold Mode (HOLD#) .................................................... 14
7.11 Accelerated Programming Operation........................... 15
8. Sector Address Table ................................................ 15
9. Command Definitions................................................ 18
9.1 Read Data Bytes (READ) ............................................ 19
9.2 Read Data Bytes at Higher
Speed (FAST_READ) .................................................. 20
9.3 Dual Output Read Mode (DOR)................................... 21
9.4 Quad Output Read Mode (QOR) ................................. 22
9.5 DUAL I/O High Performance
Read Mode (DIOR) ...................................................... 23
9.6 Quad I/O High Performance
Read Mode (QIOR) ...................................................... 24
9.7 Read Identification (RDID) ........................................... 26
9.8 Read-ID (READ_ID)..................................................... 30
9.9 Write Enable (WREN) .................................................. 31
9.10 Write Disable (WRDI)................................................... 31
9.11 Read Status Register (RDSR) ..................................... 32
9.12 Read Configuration Register (RCR) ............................ 33
9.13 Write Registers (WRR) ................................................ 34
9.14 Page Program (PP)...................................................... 36
9.15 QUAD Page Program (QPP) ....................................... 37
9.16 Parameter Sector Erase (P4E, P8E) ........................... 38
9.17 Sector Erase (SE) ......................................................... 39
9.18 Bulk Erase (BE) ............................................................ 40
9.19 Deep Power-Down (DP) ............................................... 41
9.20 Release from Deep Power-Down (RES)....................... 42
9.21 Clear Status Register (CLSR)....................................... 43
9.22 OTP Program (OTPP)................................................... 44
9.23 Read OTP Data Bytes (OTPR) ..................................... 44
10. OTP Regions ............................................................... 45
10.1 Programming OTP Address Space............................... 45
10.2 Reading OTP Data ....................................................... 45
10.3 Locking OTP Regions ................................................... 45
11. Power-up and Power-down........................................ 48
12. Initial Delivery State.................................................... 49
13. Program Acceleration via W#/ACC Pin..................... 49
14. Electrical Specifications............................................. 50
14.1 Absolute Maximum Ratings .......................................... 50
15. Operating Ranges ....................................................... 50
16. DC Characteristics...................................................... 51
17. Test Conditions ........................................................... 52
18. AC Characteristics...................................................... 53
18.1 Capacitance .................................................................. 54
19. Physical Dimensions .................................................. 56
19.1 SO3 016 — 16-pin Wide Plastic Small
Outline Package (300-mil Body Width) .........................56
19.2 WNF 008 — WSON 8-contact (6 x 8 mm)
No-Lead Package .........................................................57
19.3 FAB024 — 24-ball Ball Grid Array
(6 x 8 mm) package ......................................................58
19.4 FAC024 — 24-ball Ball Grid Array
(6 x 8 mm) package ......................................................59
20. Revision History.......................................................... 60
Document History ...............................................................60
Sales, Solutions, and Legal Information ..........................62
Worldwide Sales and Design Support ...........................62
Products ........................................................................62
PSoC® Solutions ..........................................................62
Cypress Developer Community .....................................62
Technical Support .........................................................62
Document Number: 002-00649 Rev. *I
Page 3 of 62










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