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PDF 74LVC169 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC169 | |
| Descripción | Presettable synchronous 4-bit up/down binary counter | |
| Fabricantes | NXP Semiconductors | |
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74LVC169
Presettable synchronous 4-bit up/down binary counter
Rev. 05 — 8 June 2009
Product data sheet
1. General description
The 74LVC169 is a synchronous presettable 4-bit binary counter which features an
internal look-ahead carry circuitry for cascading in high-speed counting applications.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that
the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by
the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with asynchronous
(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the
LOW-to-HIGH transition of the clock.
The counter is fully programmable; that is, the outputs may be preset to any number
between 0 and its maximum count. Presetting is synchronous with the clock and takes
place regardless of the levels of the count enable inputs. A LOW level on the parallel
enable (pin PE) input disables the counter and causes the data at the Dn input to be
loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of
the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the
counter counts up, when LOW, it counts down.
The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous
applications without additional gating. Instrumental in accomplishing this function are two
count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both
count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed
forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a
LOW-level output pulse with a duration approximately equal to a HIGH level portion of
pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded
stages.
The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing
the control of data input signals in either state of the clock. The only requirement is that
the various inputs attain the desired state at least a set-up time before the next
LOW-to-HIGH transition of the clock and remain valid for the recommended hold time
thereafter.
The parallel load operation takes precedence over the other operations, as indicated in
the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters
the flip-flops on the next LOW-to-HIGH transition of the clock.
1 page  
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
5. Pinning information
5.1 Pinning
74LVC169
U/D 1
CP 2
D0 3
D1 4
D2 5
D3 6
CEP 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9 PE
001aaa644
Fig 4. Pin configuration SO16 and
(T)SSOP16 package
terminal 1
index area
74LVC169
CP 2
D0 3
D1 4
D2 5
D3 6
CEP 7
GND(1)
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
001aaa682
Transparent top view
(1) The die substrate is attached to this pad using
conductive die material. It can not be used as a supply
pin or input.
Fig 5. Pin configuration DHVQFN16 package
5.2 Pin description
Table 2. Pin description
Symbol
Pin
U/D 1
CP 2
D0 to D3
3, 4, 5, 6
CEP
7
GND
8
PE 9
CET
10
Q0 to Q3
14, 13, 12, 11
TC 15
VCC
16
Description
up/down control input
clock input (LOW-to-HIGH, edge-triggered)
data input
count enable input (active LOW)
ground (0 V)
parallel enable input (active LOW)
count enable carry input (active LOW)
flip-flop output
terminal count output (active LOW)
supply voltage
74LVC169_5
Product data sheet
Rev. 05 — 8 June 2009
© NXP B.V. 2009. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
fmax maximum
frequency
see Figure 8
VCC = 2.7 V
150 -
-
tsk(0)
CPD
output skew time
power dissipation
capacitance
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
per input pin; VI = GND to VCC
VCC = 3.0 V to 3.6 V
150
[3] -
[4]
-
200
-
20
-
1.0
-
−40 °C to +125 °C Unit
Min Max
150 - MHz
150 - MHz
- 1.5 ns
- - pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
∑(CL × VCC2 × fo) = sum of outputs
11. Waveforms
VI
CP input
GND
VOH
Qn, TC output
VOL
1/ fmax
VM
tW
t PHL
VM
t PLH
001aaa651
Fig 8.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
74LVC169_5
Product data sheet
Rev. 05 — 8 June 2009
© NXP B.V. 2009. All rights reserved.
11 of 22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 74LVC169.PDF ] | |
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