74AHC2G00-Q100 PDF даташит
Спецификация 74AHC2G00-Q100 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Dual 2-input NAND gate». |
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Детали детали
Номер произв | 74AHC2G00-Q100 |
Описание | Dual 2-input NAND gate |
Производители | NXP Semiconductors |
логотип |
14 Pages
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74AHC2G00-Q100;
74AHCT2G00-Q100
Dual 2-input NAND gate
Rev. 1 — 21 March 2013
Product data sheet
1. General description
The 74AHC2G00-Q100; 74AHCT2G00-Q100 are high-speed Si-gate CMOS devices.
They provide two 2-input NAND gates.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low power dissipation
Balanced propagation delays
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G00DP-Q100 40 C to +125 C TSSOP8
74AHCT2G00DP-Q100
74AHC2G00DC-Q100 40 C to +125 C VSSOP8
74AHCT2G00DC-Q100
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
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NXP Semiconductors
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
4. Marking
Table 2. Marking
Type number
74AHC2G00DP-Q100
74AHCT2G00DP-Q100
74AHC2G00DC-Q100
74AHCT2G00DC-Q100
Marking code[1]
A00
C00
A00
C00
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
1Y
1B
2A
2Y
2B
001aah748
Fig 1. Logic symbol
&
&
001aah749
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
B
A
Y
mna099
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
2 of 14
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NXP Semiconductors
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
6. Pinning information
6.1 Pinning
$+&*4
$+&7*4
$
%
<
*1'
9&&
<
%
$
DDD
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
VCC
Pin description
Pin
1, 5
2, 6
4
7, 3
8
7. Functional description
Description
data input
data input
ground (0 V)
data output
supply voltage
Table 4.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
Output
nY
H
H
H
L
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
3 of 14
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74AHC2G00-Q100 | Dual 2-input NAND gate | NXP Semiconductors |
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